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web: www.galileot.com email: info@galileot.com tel: (408)451-1400 fax: (408)451-1404 system controller with pci interface for r4xxx/ r5000 family cpus GT-64010A preliminary revision 1.1 december 1996 features note: always contact galileo technology for possible updates before starting a design. galileo technology tm ? integrated system controller with pci bus interface for high performance embedded controller applications ? supports the r4600/4650/4700/r5000 cpus ? up to 50mhz cpu bus frequency ? 64 byte write buffer - 64-bit wide - 8 levels deep ? 256kb or 512kb zero-wait-state secondary cache support by using gt-64012 (r4600/r4700) ? dram controller - page mode and edo drams - 512mb address space - 256kb-16mb device depth - 1- 4 banks supported directly - 32-bit or 64-bit data width - different size for each bank ? device controller - 5 chip selects - programmable timing for each chip select - supports several types of standard memories (rom / flash / sram) and i/o controllers - up to 160mb address space - external wait support - 8-,16-,32- and 64-bit width device (and boot) sup- port ? external parity support for user selected banks of dram and devices ? dma controller - four independent channels - chaining via linked lists of records - byte alignment on source and destination - transfers through a 32-byte internal fifo - moves data between pci, memory, and devices ? pci bus - fully compatible with pci 2.1 specification - high performance pci interfaces via 96-bytes of posted write and read prefetch buffers - 32-bit pci master and slave operations - provides clock speed of up to 33mhz with no wait states on pci (asynchronous from cpu bus) - supports burst operations on pci for efficient data transfer - supports doorbells between host and pci - supports flexible byte swapping - no need for cpu intervention. - synchronization barrier support from cpu to pci and from pci to cpu. ? host to pci bridge - translates cpu cycles into pci i/o or memory cycles - generates configuration interrupt acknowledge and special cycles on pci ? pci to main memory bridge - supports fast back-to-back transactions - flexible address mapping of both dram and devices from pci side - supports memory and i/o transactions to internal configuration registers - supports locked operations ? pci configuration registers are accessed from both cpu and pci side ? three 24-bit wide and one 32-bit wide timers/counters ? 5v operation (3.3v operation using inexpensive sup- port components ? 256 pqfp or 272 ball-bga r4xxx cpu dram flash GT-64010A scsi network pci bus other sysad bus address & control data data bypass 32 32 64 i/o
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 2 revision 1.1 galileo technology tm 1. overview the GT-64010A is a highly integrated system controller that supports middle to high performance embedded control applications with state-of-the-art 64-bit mips processors, while significantly reducing their cost, complexity, device count, and board space. the architecture of the chip supports several optional system architectures for different applications and cost/perfor- mance points. it is possible to design a powerful system with minimal glue logic, or add commodity logic (controlled by the GT-64010A) for differentiated system architectures that attain higher performance. the GT-64010A has a three bus architecture: a) 64-bit interface to the cpu, b) 32-bit interface to the memory subsystem, with a bypassing option to create a 64-bit path to the cpu, c) 32-bit interface to the pci bus. the three buses are de-coupled from each other in most accesses, enabling concurrent operation of the cpu, pci devices, and accesses to memory. for example, the cpu can write to the on-chip write buffer, a dma agent can move data from dram to its own buffers, and a pci device can write into an on-chip fifo at the same time. 1.1 processor interface the GT-64010A supports without glue logic the idt/mips family of r4xxx and r5000 orion processors. it supports bus frequencies of up to 50mhz, while the processor can operate internally at 80 to 200mhz. the GT-64010A has a deep write buffer with the ab ility to absorb several write transactions from the cpu. for systems that want to increase performance even more, the GT-64010A supports the ga lileo gt-64012 secondary cache controller. systems with cpus that run internally at 3x or more of the external frequency can particularly benefit from this option. 1.2 dram and device interface the GT-64010A has a flexible dram controller. it supports edo (hyperpage) as well as standard page mode drams. with 60ns standard drams, the GT-64010A can return data at 7-2-2-2 to the cpu (four wait states to the first access). the dram controller supports different depth devices in each bank for base configuration at manufacturing, and allow- ing for field upgrades by end users. it supports 32-bit wide drams for high granularity in applications where small memory size is desirable, or 64-bit wide dram where higher memory performance is needed. the GT-64010A memory controller supports different types of memory and i/o devices. it has the control signals and the timing programmability to s upport devices like flash, eproms, srams, fifos, and i/o controllers, from 8-bit to 64-bit width. parity generation and checking is supported externally and is optional for each bank of dram or any other device on the memory bus. 1.3 pci interface the GT-64010A interfaces directly with the pci bus. it can be either a master initiating a pci bus operation or a target responding to a pci bus operation. the GT-64010A incorporates 96-bytes of posted write and read prefetch buffers for efficient data transfer between the cpu/dma to pci and pci to main memory. the GT-64010A becomes a pci bus master when the cpu or the internal dma engine initiates a bus cycle to a pci device. it translates the cpu cycle into the appropriate pci bus cycle. these cycles can be either memory, interrupt acknowledge, special, i/o, or configuration cycles. the GT-64010A acts as a target when a pci device initiates a memory access (or an i/o access in the case of internal registers). it responds to all memory read/write accesses, as well as to all configuration and i/o cycles in the case of internal registers. the GT-64010A contains the required pci configuration registers. all the internal registers, including the pci configu-
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 3 revision 1.1 galileo technology tm ration registers, can be accessed from both the cpu and the pci. the GT-64010A can also act as a pci to memory bridge, even without the presence of the cpu. 1.4 dma engines the GT-64010A incorporates four high performance dma engines. each dma engine has the capab ility to transfer data between pci devices and main memory or between devices residing on the 32-/64-bit memory bus. the dma uses an internal 32-byte fifo for temporary storage of dma data. source and destination addresses can be non- aligned on any byte address boundary. the dma channels can be programmed by the cpu or by pci masters, or with- out cpu intervention via a linked list of records that is loaded by the dma controller into the channels working set when a dma transaction ends. the dma supports increment/decrement/hold on source and destination addresses independently. 2. ordering information please use the part numbers in the table below when placing orders for gt-64010 devices. package type part number 256 pin pqfp GT-64010A-p 272 pin bga GT-64010A-b
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 4 revision 1.1 galileo technology tm 3. pin information 3.1 logic symbol validout* validin* wrrdy* release* sysad syscmd[8:0] [63:0] tclk interrupt* rst* pclk req* gnt* perr* serr* lock* devsel* stop* frame* par trdy* irdy* pad[31:0] cbe[3:0]* dwr* ras[3:0]* ad[31:28]/cs[3:0]* oeo* oee* oeb ale oe64* idsel ecas[3:0]* ocas[3:0]* leo dram dma pci interface cpu interface 32 4 64 9 int* dadr[6:4]/ewr[3:1]* dadr[10:7]/owr[3:0]* ad[27:24]/dmaack[3:0]* 4 22 cstiming* lee leadro hit/dmareq[3]* dmareq[1]*/parerr* 3 4 4 4 dadr[11]/ads* ad[23:2] local address & data bus latch control GT-64010A ad[0]/bootcs* ad[1]/ devrw* leadre/dmareq[2]* dadr[0]/badr[0] 4 4 & devices dmareq[0]*/ready* dadr[1]/badr[1] dadr[2]/badr[2] dadr[3]/ewr[0] jtrst* jtms jtclk jtdi jtdo jtag
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 5 revision 1.1 galileo technology tm 3.2. pin assignment table pin name type description cpu interface release* i release interface: signals to the GT-64010A that the processor is releasing the system interface to slave state. wrrdy* o write ready: the GT-64010A signals that it can accept a proces- sor write request. validin* o valid input: the GT-64010A signals that it is driving valid data on the sysad bus, and a valid data identifier on the syscmd bus. validout* i valid output: signals that the processor is driving valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. sysad[63:0] i/o system address/data bus: a 64-bit address and data bus for communication between the processor and GT-64010A. syscmd[8:0] i/o system command/data identifier bus: a 9-bit bus for command and data identifier transmission between the processor and gt- 64010a. interrupt* i/o interrupt: an or of all the internal interrupt sources on the gt- 64010a. this pin is also sampled as an input at reset for configura- tion purposes. tclk i clock: the input clock to the GT-64010A (up to 50mhz). pci interface pclk i pci clock: it provides the timing for the pci-related bus transac- tion. the pci clock range is between 0 and 33mhz. rst* i reset: resets the GT-64010A to its initial state. this signal must be asserted for at least 10 pci clock cycles. when in the reset state, all pci output pins are put into tristate and all open drain signals are floated. pad[31:0] i/o address/data: 32-bit multiplexed pci address and data lines. dur- ing the first clock of the transaction, pad[31:0] contains a physical byte address (32 bits). during subsequent clock cycles, pad[31:0] contains data. cbe[3:0]* i/o bus command/byte enable: these are multiplexed on the same pci pins. during the address phase of the transaction, cbe[3:0]* provide the bus command. during the data phase, these lines pro- vide the byte enable. byte enable determines which bytes carry valid data. par i/o parity: calculated by the GT-64010A as an even parity bit for the pad[31:0] and cbe[3:0]* lines. frame* i/o frame: it is asserted by the GT-64010A to indicate the beginning and duration of a master transaction. frame* asserts to indicate the beginning of the cycle. while frame* is asserted, data transfer con- tinues. frame* deasserts to indicate that the next data phase is the final data phase transaction. frame* is monitored by the gt- 64010a when it acts as a target.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 6 revision 1.1 galileo technology tm irdy* i/o initiator ready: it indicates the bus masters ability to complete the current data phase of the transaction. a data phase is completed on any clock when both trdy* and irdy* are asserted. wait cycles are inserted until trdy* and irdy* are asserted together. trdy* i/o target ready: it indicates the target agents ab ility to complete the current data phase of the transaction. a data phase is completed on any clock when both trdy* and irdy* are asserted. wait cycles are inserted until trdy* and irdy* are asserted together. stop* i/o stop: it indicates that the current target is requesting the bus mas- ter to stop the current transaction. as a master, the GT-64010A responds to the assertion of stop* by disconnecting, retrying or aborting. as a target, the GT-64010A asserts stop* to retry or dis- connect. lock* i lock: it indicates an atomic operation that may require multiple transactions to complete. when the GT-64010A is a pci target, lock* is sampled on the rising edge of the pclk when frame* is asserted. if lock* is sampled asserted, the GT-64010A enters into a locked state and remains in this state until lock* is sampled deas- serted on the following rising edge of pclk, when frame* is sam- pled asserted. idsel i initialization device select: it asserts to act as a chip select during pci configuration read and write transactions. devsel* i/o device select: it is asserted by the target of the current access. when the GT-64010A is bus master, it expects the target to assert devsel* within 5 bus cycles, confirming the access. if the target does not assert devsel* within the required bus cycles, the gt- 64010a aborts the cycle. as a target, when the GT-64010A recog- nizes its transaction, it asserts devsel* in a medium speed (two cycles after the assertion of frame*). req* o bus request: it is asserted by the GT-64010A to indicate to the bus arbiter that it desires use of the bus. gnt* i bus grant: it asserts to indicate to the GT-64010A that access to the bus is granted. perr* i/o parity error: it asserts when a data parity error is detected. serr* o system error: it asserts when a serious system error (not neces- sarily a pci error) is detected. the GT-64010A asserts the serr* two cycles after the fa iling address. int* o interrupt request: it is asserted by the GT-64010A when one of the unmasked internal interrupt sources is asserted. dram & devices dwr* o dram write: it is low when the GT-64010A writes to the dram. dadr[0]/badr[0] o dram addr ess 0 / burst address 0: this pin has two functions. in an access to a dram bank, this pin functions as a dram address bit. in write and read accesses from devices that are 8-bit wide (e.g. boot rom), this pin functions as byte address 0 in the packing process of data into 64-bits. in accesses to a word wide (32-bit) device, this bit functions as address 0 in a burst access (equivalent to sysad[2]). not used for 16/64 bit devices. pin name type description
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 7 revision 1.1 galileo technology tm dadr[1]/badr[1] o dram addr ess [1] / burst address [1]: in dram accesses, this pin functions as an address bit. in read accesses to devices that are 8-, or 16-bit wide, badr[2:1] function as a half word address in the packing process of data into 64 bits. in accesses to a 32-bit bank, badr[2:1] function as part of the (two msb) burst address bits of an address into an eight word line or when packing/unpacking a 64-bit access (equivalent to sysad[4:3]). in accesses to a 64-bit bank, badr[2:1] function as the two burst address bits of a four double word line (equivalent to sysad[4:3]). dadr[2]/badr[2] o dram addr ess [2] / burst address [2]: in dram accesses, this pin functions as an address bit. in read access to devices that are 8- or 16-bit wide, badr[2:1] function as a half word address in the packing process of data into 64 bits. in accesses to a 32-bit bank, badr[2:1] function as part of the (two msb) burst address bits of an address into an eight word line or when packing/unpacking a 64-bit access (equivalent to sysad[4:3]). in accesses to a 64-bit bank, badr[2:1] function as the two burst address bits of a four double word line (equivalent to sysad[4:3]). dadr[3]/ewr[0]* o dram addr ess [3] / even bank byte write [0]: in dram accesses this pin functions as dram address. in device writes it functions as a byte write enable indication to the even bank byte 0. dadr[6:4]/ ewr[3:1]* i/o dram addr ess [6:4] / even bank byte write [3:1]: in dram accesses these pins function as dram address. in device writes, they function as byte write enable indications to the even bank bytes [3:1]. these pins are sampled as inputs at reset for configura- tion purposes. dadr[10:7]/ owr[3:0]* i/o dram addr ess [10:7] / odd bank byte write [3:0]: in dram accesses these pins function as dram address. in device writes, they function as byte write enable indications to the odd bank bytes [3:0]. these pins are sampled as inputs at reset for configuration purposes. dadr[11]/ads* i/o dram addr ess [11] / address strobe: in dram accesses this pin functions as a dram address. in device accesses it is active for one cycle when the address for the device is on the ad bus. optionally, this pin is software configurable to only behave as ads* via bit 17 of the dram configuration register. this pin is sampled as an input at reset for configuration purposes. ras[3:0]* o row address select: supports four banks of dram. the dram banks can be 32-(36-) bit or 64-(72-) bit wide. ecas[3:0]* o even column address select: supports byte writes/reads to the even bank of the dram. ocas[3:0]* o odd column address select: supports byte writes/reads to the odd bank of the dram. local ad bus ad[31:28]/cs[3:0]* i/o data [31:28] / chip select [3:0]: in the data phase, the pins func- tion as data bits [31:28]. in the address phase, device chip selects are valid (and should be latched). the chip selects need to be qualified with the cstiming* signal. latching is done via ale. pin name type description
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 8 revision 1.1 galileo technology tm ad[27:24]/ dmaack[3:0]* i/o data [27:24] / dma acknowledge[3:0]: in the data phase, the pins function as data bits [27:24]. in the address phase, dma acknowl- edges are valid (and should be latched). they need to be qualified with the cstiming* signal. latching is done via ale. ad[23:2] i/o address/data[23:2]: multiplexed address and data bus to the dram (data only) and the devices (address and data). ad[1]/devrw* i/o data [1] / device read-write: in the data phase it is data bit 1. in the address phase, it indicates if an access to a device is a read (1) or a write (0). latching is done via ale. ad[0]/bootcs* i/o data [0]/ boot chip select: in the data phase it is data bit 0. in the address phase, it is the boot device chip select. latching is done via ale. cstiming* o chip select timing: active for the number of cycles that the device that is currently being accessed was programmed to. used to qual- ify the cs[3:0]*, bootcs and the dmaack[3:0]* signals. latch control ale o address latch enable: used to latch the address, bootcs*, cs[3:0]*, devrw* and dmaack[3:0]* from the ad bus. leo o latch enable odd: used to latch data to or from the odd bank devices. lee o latch enable even: used to latch data to or from the even bank devices. oeo* o output enable odd: output data from the latch of the odd bank to the ad bus. oee* o output enable even: output data from the latch of the even bank to the ad bus. oeb o output enable write: output data from the latch of the ad bus to the memory bus. this signal is only active during writes to dram or devices, and its polarity is programmable at reset. oe64* o output enable 64-bit: output enable for the latch from memory to the sysad bus. leadro o latch enable address odd: used to latch the dram address and device burst address of the odd bank. leadre/ dmareq[2]* i/o latch enable address even / dma request: multiplexed signal that can be used to latch the dram address and device address of the even bank or, as a dma request indication by an external device. its function is designated at reset. dma hit/dmareq[3]* i hit / dma request: this pin can be configured as a hit indication from a secondary cache device or as a dma request indication by an external device, depending on the setting of bit 9 of the cpu interface configuration register. dmareq[1]*/ parerr* i dma request [1] / dma parity error: dma request indication by an external device or parity error indication by external logic. the function of this pin is programmable at reset. pin name type description
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 9 revision 1.1 galileo technology tm 4. functional description 4.1 cpu interface the GT-64010A supports the r4xxx and r5000 family of 64-bit cpus. it supports the idt r4600, r4650, r4700, and r5000 at up to 50mhz bus frequency. the GT-64010A has a 64 byte, 8 level deep, write buffer that can absorb up to four cpu write transactions. standard r4xxx write and the r4600 pipelined write modes are supported (the r4600 re- issue option is not supported). cpu read requests are supported via two possible paths: reads from the pci, and from 32-bit wide (or less) devices are performed through the GT-64010A; cpu reads from 64-bit devices bypass the gt- 64010a through an external latch that is controlled by the GT-64010A. the interface supports the big and little endian options of the cpu. 4.2 secondary cache support the gt- 64010 supports the gt- 64012 secondary cache controller for the r4600/r4700 cpus. the hit input pin indicates to the GT-64010A if the current cpu read can be serviced from the cache memory or it needs to be serviced by the GT-64010A. flush and invalidate operations on the secondary cache are ignored by the GT-64010A. 4.3 address space decode the GT-64010A uses a distributed address decoding scheme. each master unit (cpu or pci) has a separate address decoding logic and registers. the dma controller uses the address mapping of the cpu interface. address space for the different system resources is programmable and can be programmed differently in each master unit. the system resources are divided into seven groups: ras[1:0], ras[3:2], cs[2:0], cs[3] & bootcs, internal, pci i/o, and pci memory. each group can have a minimum of 2 mbytes and a maximum of 256 mbytes of address space. the individual devices in the device groups (e.g. ras[0]) are further sub decoded to 1 mbyte resolution. the sub decoding is not distributed in the different master units but is centralized in the device controller unit. the system resources groups can be mapped into a 64 gbyte address space for cpu accesses and into 4 gbyte address space for the dma and pci accesses. when the cpu tries to access an address that is not supported, the GT-64010A w ill latch the address into the bus error registers, and w ill issue a bus error (over syscmd[5]) if the access was a r ead access, and an interrupt if it was a read or write access. dmareq[0]*/ ready* i dma request [0] / ready: this pin has two functions: it serves as a dma request indication by an external device, or as a cycle extender (when inactive during a device access, an access w ill extend until ready* is asserted). the function of this pin is program- mable at reset. jtag jtrst* i jtag reset: asynchronous reset to test logic. jtclk i jtag clock: clock for test logic. jtms and jtdi are received on the rising edge, jtdo is driven from the fa lling edge. this signal determines the shifting rate. jtms i jtag mode select: a broadcast signal which controls test logic operation. jtdi i jtag data in: serial data input. jtdo o jtag data out: serial data output. tri-state changes on negative change of jtclk. pin name type description
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 10 revision 1.1 galileo technology tm 4.4 parity support memory or device parity generation and checking is supported with external logic. the external logic should generate parity in write accesses to devices and memory and check parity in read accesses. when a parity error is detected by the external logic it needs to drive the parerr* pin of the GT-64010A. the GT-64010A has a programmable parity integ- rity bit for each bank, which indicates if parity is supported. in read accesses by the cpu from a 72-bit bank dram or device, the GT-64010A w ill assert syscmd[4] to indicate to the cpu if it needs to check parity for the current access. in this case the GT-64010A relies on the cpu parity checking mechanism. in cpu read accesses from a 32-bit device or memory, the GT-64010A w ill not assert syscmd[4] even if the bank that was accessed has the parity integrity bit set. if a parity error is detected in this case (indicated by par- err*), the GT-64010A w ill return the data with syscmd[5] asserted and w ill cause a parity error interrupt. in dma read accesses, detection of a parity error from a bank with the parity integrity bit set, w ill cause an interrupt. in the case of pci read accesses, the GT-64010A w ill assert serr* if the bank that data was read from has the parity integrity bit set, and w ill assert a parity error interrupt. the gt- 64010a w ill generate and check word (32- bits) parity on data that is read from the pci with compliance to the pci requirements for every transaction. a parity error detection on the pci will cause the assertion of perr*. for the c onnection of memory buses, refer to section 8. 4.5 memory control the gt64010a system can be assembled in different configurations which are up to the user. there are two main configurations: without data latches on the ad bus, meaning that the system is implemented with a 32-bit or narrower bus, and with latches on the ad bus, which allows for 64-bit bus accesses. for details regarding the connection of memory, see section 8. 4.6 dram controller the dram controller supports page mode and edo dram. the depth of the dram devices can vary for each bank separately from 256k to 16m, and the width of each bank can be 32- or 64-bits. with these options, each dram bank size can vary from 1 mbyte to 128 mbytes. furthermore, 0.5k, 1k, 2k, and 4k refresh drams can be used, as well as asymmetric ras, cas addressing. some of the dram timing parameters are programmable to allow for different system timing optimizations. ras-to- cas delay can be programmed to two or three cycles, and cas can be low for one or two cycles. dram performance in cpu read accesses is 7-2-2-2, which means 4 wait states to first data and one wait state for each additional double word. dma and pci burst accesses can be one per clock for a maximum of 8 consecutive 32-bit words. refresh can be programmed to different frequencies of occurrences by the refresh counter. for example, if the refresh counter is programmed to 0x200, then at 50mhz a refresh sequence w ill occur every 10us (20ns x 200). staggered and non-staggered refresh modes are supported. in staggered mode, the four banks of dram w ill be refres hed with one cycle delay between each bank, while in non-staggered mode all four banks w ill be refres hed together. 4.7 device controller this controller has programmable timing parameters for each device bank to accommodate different device types (e.g. flash, sram, rom, i/o controllers). the devices share the local ad bus with the dram, but unlike the dram, the devices use the ad bus as a multiplexed address and data bus. in the address phase, the device controller puts on the bus 22-bits of address, four general purpose chip select signals (cs[3:0]*), one boot chip select (bootcs*), four dma acknowledge signals (dmaack[3:0]*), and an indication as to whether the access is a read or write (devrw*). a bus cycle starts by the assertion of ale and ads* for one cycle when a cs* signal and/or a dmaack* signal are active. the cs* and dmaack* need to be externally latched and qualified with cstiming*. the cstiming* signal will be valid for the programmable number of cycles of the specific cs* that is active. there are eight byte write signals, four for the even bank (ewr[3:0]*) and four for the odd bank (owr[3:0]*). the write
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 11 revision 1.1 galileo technology tm signals can be shaped by specifying the following: the number of cycles from the assertion of ads* to the first assertion of write, the number of cycles the write pulse is active (low) - could be extended by ready*, and the number of cycles the write signal is non-active between consecutive writes. the timing parameters of the write signals determine the length of active cs* (or dmaack*) signals, as well as the external latch control and burst address change timing. for read cycles, a device access time to first data (could be extended by ready*) and to the following data (could be extended by ready*) in burst accesses defines the cycle parameters. the access time determines the timing that data will be latc hed, and when the burst address w ill c hange. the device controller supports up to 8 word burst accesses. the burst address is supported by a three bit wide address bus (badr[2:0]) that is different from the multiplexed ad bus. the same bus also supports the packing of data into a 64- bit double word, in reads from devices that are 8-bits to 32-bits wide. devices that are 8-bits or 16-bits wide only are supported by partial reads (up to 64-bits). the controller supports cpu writes of 1 to 8 bytes to 8-bit or 16-bit wide devices. it supports dma/pci writes of 1 to 4 bytes to 8-bit or 16-bit wide devices. 4.7.1. ready* support the ready* pin is sampled on two different occasions: on the last rising edge of the wractive phase during a write cycle and one clock before the data is sampled to the GT-64010A during both acctofirst and acctonext phases. dur- ing all other phases ready* is not sampled by the gt64010a. if ready* is not asserted during these clocks, the wractive, acctofirst or acctonext phases are extended until ready* is asserted again. see the timing diagrams added for read and write cycles that are controlled by ready* 4.8 dma controller the dma controller can move data between devices on the ad bus, between devices on the pci bus, or between devices on the ad bus and devices on the pci bus. all dma transfers use an internal 32-byte fifo for moving data. data is transferred from the source device into the internal fifo, and from the internal fifo to the destination device. the length of each transfer of dma can be limited to 1, 2, 4, 8, 16 or 32 bytes. accesses can be non-aligned both in the source and the destination. the dma can be programmed to move up to 64 kbytes of data in each transaction. the dma controller supports chained and non-chained modes of operation. in the non-chained mode the cpu or the pci program the dma channel for each dma transaction. in chained mode, the dma controller programs itself for the next dma operation by fetching the information from a linked list of records in memory. the dma controller can be programmed to assert an interrupt in chained mode at the end of every dma transaction, or when the next pointer register is null and byte count reaches terminal count. in non-chained mode, the dma will assert an interrupt every time the byte count reaches terminal count. dma accesses can be initiated by an external request by asserting one of the four dmareq[3:0]* pins (demand mode), or by setting an internal bit in a register (block mode). accesses by the four dma channels can be prioritized via a programmable arbiter. channels 0 and 1 are in one group and channels 2 and 3 are in another group. inside each group, the priority can be fixed so a selected channel number can have a higher priority, or both can have the same priority in round-robin fashion. the same scheme applies between the two groups, they can have fixed or round-robin priority. 4.9 pci bus the GT-64010A interfaces directly with the pci bus. as a pci device, the GT-64010A can be either a master initiating a pci bus operation or a target responding to a pci bus operation. when the cpu or the internal dma machine ini- tiates a bus cycle to a pci device, the GT-64010A becomes a pci bus master and translates the cpu cycle into the appropriate pci bus cycle. the cycles are:
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 12 revision 1.1 galileo technology tm ? memory read ? memory write ? memory read line ? memory write & invalidate ? i/o read ? i/o write ? configuration read ? configuration write ? interrupt acknowledge ? special cycle as a master, the GT-64010A does not issue dual address cycles or lock cycles on the pci. memory write & invalidate and memory read line cycles are carried out when the transaction addresses the pci memory space requiring a data transfer equal to the cache line size. for details on configuration, interrupt acknowl- edge and special cycles, refer to section 3.14 (pci configuration registers). the pci posted write buffer in the GT-64010A permits the cpu to complete cpu-to-pci memory writes even if the pci bus is busy. the posted data is written to the pci device when the pci bus is available. when a pci bus master initiates an access, the GT-64010A becomes the target of the pci bus cycle and responds to the read/write access. the GT-64010A responses to the following pci cycles: ? memory read ? memory write ? memory read line ? memory read multiple ? memory write and invalidate ? i/o read ? i/o write ? configuration read ? configuration write the GT-64010A w ill lock a cache line (32-bytes) in the memory address space when responding to lock sequences on the pci bus. the GT-64010A w ill not act as a target (slave) for interrupt acknowl edge, special, and dual address cycles. the GT-64010A incorporates dual 32-bytes posted write/read prefetch buffers to allow full memory and pci bus con- currence. in every posted write cycle, the data is first written to the buffers. when a buffer f ills up (32 bytes), the data is written to the destination while the second buffer is being f illed up. i/o and configuration cycles are non-postable. the memory read multiple cycle is the only prefetchable read cycle. every time there is at least two words within the first buffer, data is being prefetched into the second buffer. in a non-prefetchable read cycle, the data is written into the second buffer after the first one gets full. the master's fifo includes 8 entries each 32 bit. during writes, it receives write data from the cpu interface or the dma unit. when the pci bus is granted, it delivers the write data to the target on the pci bus. upon receiving the first doubleword from the cpu interface or dma unit, the machine which handles the pci bus protocol is triggered to request the bus (if the GT-64010A is not already parked). once granted, the appropriate write cycle is started on the pci bus. during reads, the master's fifo receives read data from the pci bus and delivers it to the cpu interface or dma unit. upon receiving the first doubleword from the pci target, the data is forwarded to the requesting unit (cpu interface or dma unit). the GT-64010A supports sub-block ordering during cpu reads, therefore if the original read request address is not aligned to a cache line boundary, the first doubleword returned to the requesting unit w ill be delayed until it is received from the pci target, since reads across the pci bus are linear.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 13 revision 1.1 galileo technology tm the GT-64010A internal architecture allows zero wait state data transfer over the pci bus (irdy* continuously asserted) during both reads and writes. as a pci device, the GT-64010A contains all of the required pci configuration registers. these registers, as well as the GT-64010As internal registers are accessed from both the cpu and the pci bus. the GT-64010A considers some cycles as being synchronization barrier cycles. in such cycles, the GT-64010A makes sure that at the end of the cycle there remains no posted data within the chip. the slave synchronization bar- rier cycles are lock read and configuration read. if there is no posted data within the GT-64010A, the cycle ends normally. if after a retry period there is still posted data, the cycle w ill be retried. until the original cycle ends, any other (different address/command) synchronization barrier cycles w ill be retried. lock r ead is a synchronization barrier cycle which lasts during the entire lock period, i.e. when the slave is locked all configuration reads w ill be retried. also, all cycles addressed to internal registers w ill be retried until lock ends. the cpu interface treats i/o reads to pci and configuration reads as synchronization barrier cycles as well. these reads w ill be res ponded to once no posted data remains within the GT-64010A. as a target, the GT-64010A can be programmed not to respond to specific address spaces. also it can be programmed to swap or not swap bytes, dependent on transaction nature (write/read) and address space. for example, the gt- 64010a can transfer written words directly to a certain dram bank and read these words byte-swapped, independent of other banks. this allows pci to pci byte swapping without cpu intervention. 4.10 interrupt controller the interrupt controller groups all the internal interrupt sources and asserts an interrupt to the cpu or to the pci when one or more internal interrupts are asserted. there is one cause register and two mask registers. the cause register has one bit for each interrupt source. if the source asserts an interrupt, its respective bit in the cause register w ill be set. this bit can be read by the cpu or by the pci. the interrupt w ill be acknowl edged by the cpu or by the pci by resetting its bit in the cause register (writing zero to the specific bit and one to all the other bits.). each interrupt sourc e has one mask bit in the cpu mask register and one bit in the pci mask register. a zero in the cpu mask register bit will mask the interrupt from asserting an interrupt to the cpu. a zero in the pci mask register bit will mask the interrupt from asserting an interrupt to the pci. 4.11 timer/counters the GT-64010A has three 24-bit and one 32 bit timers/counters. when programmed as a counter, the counter w ill dec- rement every clock, will set an interrupt and w ill stop c ounting. in the timer mode, it w ill set the interrupt but will reload to the initial value and continue to count down. the initial value for each timer counter is programmable. write accesses are done to the timer/counter register but read accesses (from the same address) are directly from the counter outputs. 4.12 reset configuration the GT-64010A must acquire some knowledge about the system before it is configured by the software. special modes of operation are sampled on reset in order to enable the GT-64010A to function in consistence with the specific system it is used in. certain pins must be pulled up or down (4k7 recommended) externally to accomplish this. the fol- lowing configuration pins are continuously sampled from rst* assertion until 3 tclk cycles after rst* is deasserted.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 14 revision 1.1 galileo technology tm note: leadre/dmareq[2]* should be selected 0 whenever leadre is not used in the system (e.g., dram is not oper- ating in decrement mode). 4.13 jtag the GT-64010A incorporates jtag as per ieee-1149.1. the following opcodes are supported: - bypass (111) - extest (000) - sample (010) - idcode (001) the idcode register fields values in the GT-64010A are: manufacturer (11 bits) - 0x08a part number (16 bits) - 0x0146 version (4 bits) - 0x2 for the GT-64010A signal ordering of boundary chain please refer to jtag appendix, section 11.3. pin configuration function interrupt*: endianess 0- 1- big endian data format little endian data format dadr[11:10]: device boot bus width 00- 01- 10- 11 - 8 bits 16 bits 32 bits 64 bits dadr[9]: leadre/dmareq[2]* selection 0- 1- dmareq[2]* leadre dadr[8]: oeb polarity 0- 1- active low active high dadr[7]: external latches presence 0- 1- latches are present system without latches dadr[6]: reserved 0- must be sampled low dadr[5]: dmareq[1]*/parerr* selection 0- 1- dmareq[1]* (no parity) parerr* dadr[4]: dmareq[0]*/ready* selection 0- 1- ready* dmareq[0]*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 15 revision 1.1 galileo technology tm 5. register tables the GT-64010As internal registers can be accessed by the cpu or by the pci. they are memory-mapped for the cpu and memory- or i/o-mapped for the pci. the registers address is comprised of the value in the internal space decode register and the register offset. the value in the internal space decode register [14:0] is matched against bits [35:21] of the actual address; therefore, this value should be the actual address bits [35:21] shifted right once. for example, to access channel 0 dma byte count register (offset 0x800) immediately after reset*, the full address will be the default value in the internal space dec ode register which is 0x0a0 shifted left once, which gives 0x140, two zeros and the offset 0x800, to become a 36-bit address of 0x014000800. the location of the registers in the mem- ory space can be changed by changing the value programmed into the internal space decode register. for example after changing the value in the internal space decode register by writing to 0x014000068 a value of 0bd, an access to the channel 0 dma byte count register w ill be with 0x 017a00800. an access to a pci configuration register is done differently than accesses to all other registers. the access is done indirectly by writing the pci configuration register offset into the configuration address register and then reading or writing the data from/to the configuration data register. for example, to read data from the status and command reg- ister, the register offset 0x004 has to be written into the configuration address register, offset 0xcf8 (or full address from the previous example 0x0bd000cf8). then, reading from the configuration data register (offset 0xcfc), w ill return the data of the status and command register.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 16 revision 1.1 galileo technology tm 5.1 register map description offset cpu interface cpu interface configuration 0x000 processor address space ras[1:0] low decode address 0x008 ras[1:0] high decode address 0x010 ras[3:2] low decode address 0x018 ras[3:2] high decode address 0x020 cs[2:0] low decode address 0x028 cs[2:0] high decode address 0x030 cs[3] & boot cs low decode address 0x038 cs[3] & boot cs high decode address 0x040 pci i/o low decode address 0x048 pci i/o high decode address 0x050 pci memory low decode address 0x058 pci memory high decode address 0x060 internal space decode 0x068 bus error address low processor 0x070 bus error address high processor 0x078 dram and device addr ess space ras[0] low decode address 0x400 ras[0] high decode address 0x404 ras[1] low decode address 0x408 ras[1] high decode address 0x40c ras[2] low decode address 0x410 ras[2] high decode address 0x414 ras[3] low decode address 0x418 ras[3] high decode address 0x41c cs[0] low decode address 0x420 cs[0] high decode address 0x424 cs[1] low decode address 0x428 cs[1] high decode address 0x42c cs[2] low decode address 0x430 cs[2] high decode address 0x434 cs[3] low decode address 0x438 cs[3] high decode address 0x43c boot cs low decode address 0x440 boot cs high decode address 0x444 address decode error 0x470
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 17 revision 1.1 galileo technology tm dram configuration dram configuration 0x448 dram parameters dram bank0 parameters 0x44c dram bank1 parameters 0x450 dram bank2 parameters 0x454 dram bank3 parameters 0x458 device parameters device bank0 parameters 0x45c device bank1 parameters 0x460 device bank2 parameters 0x464 device bank3 parameters 0x468 device boot bank parameters 0x46c dma record channel 0 dma byte count 0x800 channel 1 dma byte count 0x804 channel 2 dma byte count 0x808 channel 3 dma byte count 0x80c channel 0 dma source address 0x810 channel 1 dma source address 0x814 channel 2 dma source address 0x818 channel 3 dma source address 0x81c channel 0 dma destination address 0x820 channel 1 dma destination address 0x824 channel 2 dma destination address 0x828 channel 3 dma destination address 0x82c channel 0 next record pointer 0x830 channel 1 next record pointer 0x834 channel 2 next record pointer 0x838 channel 3 next record pointer 0x83c dma channel control channel 0 control 0x840 channel 1 control 0x844 channel 2 control 0x848 channel 3 control 0x84c dma arbiter arbiter control 0x860 timer/counter timer /counter 0 0x850 timer /counter 1 0x854 timer /counter 2 0x858
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 18 revision 1.1 galileo technology tm 5.2 cpu interface the cpu interface configuration register determines which of the different mips write protocols is supported, as well as secondary cache issues and cpu endianess. the differences in protocol are minimal and they include support for pipelined write, etc. the GT-64010A supports the ga lileo gt-64012 secondary cache controller, and thus when the cachepres bit is set to 1, the GT-64010A w ill not service cac heable read requests if there is a hit indication from the secondary cache. the cacheopmap bits indicate which address bits w ill be used for cache flush and cache invalidate operation by the gt-64012. when the GT-64010A finds a match between a 1 in the read address and the cacheop- map bits that are set to 1, it will i gnore the access, and the gt-64012 w ill flush or invalidate the sec ondary cache. for example, setting bit 8 to 1 indicates that sysad[35] is connected to one of the two gt-64012s tagop inputs, setting bit 7 to 1 indicates that sysad[34] is connected to one of them, etc. timer /counter 3 0x85c timer /counter control 0x864 pci internal command 0xc00 time out & retry 0xc04 ras[1:0] bank size 0xc08 ras[3:2] bank size 0xc0c cs[2:0] bank size 0xc10 cs[3] & boot cs bank size 0xc14 serr mask 0xc28 interrupt acknowledge 0xc34 configuration address 0xcf8 configuration data 0xcfc interrupts interrupt cause 0xc18 cpu mask 0xc1c pci mask 0xc24 pci configuration device and vendor id 0x000 status and command 0x004 class code and revision id 0x008 header type, latency timer, cache line 0x00c ras[1:0] base address 0x010 ras[1:0] swapped base address 0x028 ras[3:2] base address 0x014 ras[3:2] swapped base address 0x02c cs[2:0] base address 0x018 cs[3] & boot cs base address 0x01c cs[3] & boot cs swapped base address 0x030 internal registers memory mapped base address 0x020 internal registers i/o mapped base address 0x024 base address registers enable 0x034 interrupt pin and line 0x03c
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 19 revision 1.1 galileo technology tm cpu interface configuration, offset: 0x000 5.3 processor address space the decode address registers determine which physical device group w ill be accessed w hen the cpu issues an address. the decode to the specific bank (ras or cas) in each group is done in the memory control unit. the address decoding is done by comparing bits 35:28 of the address to bits 14:7 of the low field of all the low decode registers to find a match, and by comparing address bits 27:21 to be greater than or equal to bits 6:0 of the low fields, and less than or equal to the high field. when an address is out of range (of all the decode address registers), the cpu w ill be interrupted during a write access and a bus error w ill be asserted during a r ead access. the invalid address w ill be cap- tured in the bus error address low and high registers. the dma controller uses the processors address decoding, with the exception of bits 35:32. ras[1:0] low decode address, offset: 0x008 ras[1:0] high decode address, offset: 0x010 bits field name function initial value 8:0 cacheopmap cache operation mapping. indicates which address bits will be used for cache flush and cache invalidate operation by the gt-64012. bits 8:0 correspond to sysad[35:27]. 0x0 9 cachepres secondary cache support. 0 - gt-64012 not present 1 - gt-64012 present 0x0 10 reserved must be 0. 0x0 11 writemod write mode. 0 - pipelined writes mode 1 - r4xxx mode (2 dead-cycles minimum between consecutive address-phases) 0x0 12 endianess byte orientation. 0 - big endian 1 - little endian sampled at reset via the interrupt* pin bits field name function initial value 14:0 low dram banks 1 and 0 w ill be accessed w hen the decoded addresses are between low and high. 0x0000 bits field name function initial value 6:0 high dram banks 1 and 0 w ill be accessed w hen the decoded addresses are between low and high. 0x07
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 20 revision 1.1 galileo technology tm ras[3:2] low decode address, offset: 0x018 ras[3:2] high decode address, offset: 0x020 cs[2:0] low decode address, offset: 0x028 cs[2:0] high decode address, offset: 0x030 cs[3] & boot cs low decode address, offset: 0x038 cs[3] & boot cs high decode address, offset: 0x040 bits field name function initial value 14:0 low dram banks 3 and 2 w ill be accessed w hen the decoded addresses are between low and high. 0x0008 bits field name function initial value 6:0 high dram banks 3 and 2 w ill be accessed w hen the decoded addresses are between low and high. 0x0f bits field name function initial value 14:0 low device banks 2, 1 and 0 w ill be accessed w hen the decoded addresses are between low and high. 0x00e0 bits field name function initial value 6:0 high device banks 2, 1 and 0 w ill be accessed w hen the decoded addresses are between low and high. 0x70 bits field name function initial value 14:0 low device bank 3 and the boot bank w ill be accessed when the decoded addresses are between low and high. 0x00f8 bits field name function initial value 6:0 high device bank 3 and the boot bank w ill be accessed when the decoded addresses are between low and high. 0x7f
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 21 revision 1.1 galileo technology tm pci i/o low decode address, offset: 0x048 pci i/o high decode address, offset: 0x050 pci memory low decode address, offset: 0x058 pci memory high decode address, offset: 0x060 internal space decode, offset: 0x068 bus error address low processor, offset: 0x070 bits field name function initial value 14:0 low the pci i/o address space w ill be accessed w hen the decoded addresses are between low and high. 0x0080 bits field name function initial value 6:0 high the pci i/o address space w ill be accessed w hen the decoded addresses are between low and high. 0x0f bits field name function initial value 14:0 low the pci memory address space w ill be accessed when the decoded addresses are between low and high. 0x0090 bits field name function initial value 7:0 high the pci memory address space w ill be accessed when the decoded addresses are between low and high. 0x1f bits field name function initial value 14:0 intdecode registers inside the GT-64010A w ill be accessed when sysad bits 35:21 match the value programmed in bits 14:0. 0x00a0 bits field name function initial value 31:0 ilegloadd this register captures bits 31:0 of an illegal 64-bit address. 0x00000000
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 22 revision 1.1 galileo technology tm bus error address high processor, offset: 0x078 5.4 dram and device address space the decode address registers determine which physical device w ill be accessed w hen the cpu, dma, or pci issue an address. the address decoding is done by comparing address bits 27:20 to be greater than or equal to the value in the low fields, and less than or equal to the value in the high fields. in case that no match occurs, an interrupt w ill be issued and the address causing the error w ill be latc hed in the address decode error register. this error can occur when the cpu or pci decoding matches the address while the sub-decoding done in the memory unit doesnt match any of the addresses defined in the address space. ras[0] low decode address, offset: 0x400 ras[0] high decode address, offset: 0x404 ras[1] low decode address, offset: 0x408 ras[1] high decode address, offset: 0x40c ras[2] low decode address, offset: 0x410 bits field name function initial value 3:0 ileghiadd this register captures bits 35:32 of an illegal 64-bit address. 0x0 bits field name function initial value 7:0 low dram bank 0 w ill be accessed w hen the decoded addresses are between low and high. 0x00 bits field name function initial value 7:0 high dram bank 0 w ill be accessed w hen the decoded addresses are between low and high. 0x07 bits field name function initial value 7:0 low dram bank 1 w ill be accessed w hen the decoded addresses are between low and high. 0x08 bits field name function initial value 7:0 high dram bank 1 w ill be accessed w hen the decoded addresses are between low and high. 0x0f bits field name function initial value 7:0 low dram bank 2 w ill be accessed w hen the decoded addresses are between low and high. 0x10
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 23 revision 1.1 galileo technology tm ras[2] high decode address, offset: 0x414 ras[3] low decode address, offset: 0x418 ras[3] high decode address, offset: 0x41c cs[0] low decode address, offset: 0x420 cs[0] high decode address, offset: 0x424 cs[1] low decode address, offset: 0x428 cs[1] high decode address, offset: 0x42c cs[2] low decode address, offset: 0x430 bits field name function initial value 7:0 high dram bank 2 w ill be accessed w hen the decoded addresses are between low and high. 0x17 bits field name function initial value 7:0 low dram bank 3 w ill be accessed w hen the decoded addresses are between low and high. 0x18 bits field name function initial value 7:0 high dram bank 3 w ill be accessed w hen the decoded addresses are between low and high. 0x1f bits field name function initial value 7:0 low device bank 0 w ill be accessed w hen the decoded addresses are between low and high. 0xc0 bits field name function initial value 7:0 high device bank 0 w ill be accessed w hen the decoded addresses are between low and high. 0xc7 bits field name function initial value 7:0 low device bank 1 w ill be accessed w hen the decoded addresses are between low and high. 0xc8 bits field name function initial value 7:0 high device bank 1 w ill be accessed w hen the decoded addresses are between low and high. 0xcf bits field name function initial value 7:0 low device bank 2 w ill be accessed w hen the decoded addresses are between low and high. 0xd0
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 24 revision 1.1 galileo technology tm cs[2] high decode address, offset: 0x434 cs[3] low decode address, offset: 0x438 cs[3] high decode address, offset: 0x43c boot cs low decode address, offset: 0x440 boot cs high decode address, offset: 0x444 address decode error, offset: 0x470 5.5 dram configuration the dram configuration register specifies refresh parameters and optional usage of two of the GT-64010A pins related to the dram controller. the time between refresh cycles is programmable, with the option to refresh all the banks at the same time or in staggered fashion. the pin functionality of dram address bit 11 can be programmed to be ads* only for systems that do not have deep drams. this pin can also be programmed to be ads* in device accesses, and to function as dram address 11 in dram accesses. bits field name function initial value 7:0 high device bank 2 w ill be accessed w hen the decoded addresses are between low and high. 0xdf bits field name function initial value 7:0 low device bank 3 w ill be accessed w hen the decoded addresses are between low and high. 0xf0 bits field name function initial value 7:0 high device bank 3 w ill be accessed w hen the decoded addresses are between low and high. 0xfb bits field name function initial value 7:0 low boot bank w ill be accessed w hen the decoded addresses are between low and high. 0xfc bits field name function initial value 7:0 high boot bank w ill be accessed w hen the decoded addresses are between low and high. 0xff bits field name function initial value 31:0 erraddr the addresses of accesses to invalid address ranges (those not in the range programmed in the dram or device decode registers) w ill be captured in this regis- ter. 0xffffffff
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 25 revision 1.1 galileo technology tm dram configuration, offset: 0x448 5.6 dram parameters dram timing parameters, bank width, 32-bit wide bank location, parity support, and refresh support for different dram sizes, can be set for each dram bank independently. the number of cycles cas* is active (low) in read or write accesses can be programmed to one or two cycles. the number of cycles between the cycle ras* becomes active and the cycle cas* becomes active in reads or writes is programmable as well. bits field name function initial value 13:0 refintcnt refresh interval count value. 0x0200 15:14 reserved 16 stagref staggered refresh. 0 - staggered refresh 1- all banks are refreshed together 0x0 17 adsfunct defines the function of the dadr[11]/ads* pin. 0 - ads* in device accesses & dram address [11] in dram accesses. 1 - ads* only 0x0 18 dramlatch sets the latch operation mode. 0 -the latch control signals are active. 1 - the external data latches are transparent in dram accesses when cas is programmed to be one cycle long 0x0
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 26 revision 1.1 galileo technology tm dram bank0 parameters, offset: 0x44c dram bank1 parameters, offset: 0x450 dram bank2 parameters, offset: 0x454 dram bank3 parameters, offset: 0x458 bits field name function initial value 0 caswr the number of cycles cas* is low in a write access. 0 - one cycle 1 - two cycles 0x1 1 rastocaswr the number of cycles between ras* going active and cas* going active in a write access. 0 - two cycles 1 - three cycles 0x1 2 casrd the number of cycles cas* is low in a read access. 0 - one cycle 1 - two cycles 0x1 3 rastocasrd the number of cycles between ras* going active and cas* going active in a read access. 0 - two cycles 1 - three cycles 0x1 5:4 refresh dram type support. 00 - 1/2k refresh (9 bits row, 9 to 12 bits column) 01 - 1k refresh (10 bits row, 9 to 12 bits column) 10 - 2k refresh (11 bits row, 9 to 12 bits column) 11 - 4k refresh (12 bits row, 9 to 12 bits column) 0x0 6 bankwidth width of dram bank. 0- 32 (36) bit wide dram 1- 64 (72) bit wide dram 0x0 7 bankloc location of a 32-bit wide bank. 0- even 1- odd 0x0 8 parity parity support for the bank. 0- no parity support 1- parity supported 0x0 bits field name function initial value 8:0 various fields function as in dram bank0. 0xf bits field name function initial value 8:0 various fields function as in dram bank0. 0xf bits field name function initial value 8:0 various fields function as in dram bank0. 0xf
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 27 revision 1.1 galileo technology tm 5.7 device parameters device parameters can be different for each bank. the shape of the different control signals that are active in a device access can be programmed. the access time of the device (in number of cycles) during read accesses should be pro- grammed into the acctofirst field, to set the time that data from the device will be latc hed into the external latch. acctonext should be programmed for the time that data from the device can be latched in consecutive accesses dur- ing burst accesses. to prevent bus contention, the turnoff field specifies the number of cycles (from the deassertion of cstiming*) to the beginning of the next bus transaction. the write signals pulse should be shaped as well. the param- eters specify the number of cycles from the beginning of the cycle to the assertion of the write signals (adstowr), the number of cycles the write is active (wractive), and the number of cycles the write signals are inactive (wrhigh) between consecutive writes in a burst access. device width can be programmed to 8-, 16-, 32-, or 64-bits (default is 32-bits except for the boot bank). the device controller can pack data during reads from a word that is less than 64-bits wide. for devices that are less then 64-bits, the device can be located in the odd or the even bank. devices that are 8-bits or 16-bits wide only support partial reads (up to 64-bits). performance when reading from a device can be optimized to save a cycle in each access by making the latch trans- parent for devices that can supply the data to the GT-64010A on time, without the need to be latched.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 28 revision 1.1 galileo technology tm device bank0 parameters, offset: 0x45c device bank1 parameters, offset: 0x460 bits field name function initial value 2:0 turnoff the number of cycles between the deassertion of devoe* (an externally extracted signal which is the logical or between cstiming* and inverted devrw*) to a new ad bus cycle. 0x7 6:3 acctofirst the number of cycles in a read access from the assertion of cs* to the cycle that the data w ill be latched (by the external latches). can be extended via the ready* pin. 0xf 10:7 acctonext the number of cycles in a read access from the cycle that the first data was latched to the cycle that the next data will be latc hed (in burst accesses). can be extended via the ready* pin. 0xf 13:11 adstowr the number of cycles from ads* active to the asser- tion of ewr* or owr*. 0x7 16:14 wractive the number of cycles ewr* or owr* are active. can be extended via the ready* pin. 0x7 19:17 wrhigh the number of cycles between deassertion and assertion of ewr* or owr*. 0x7 21:20 devwidth device width. 00 - 8 bits 01- 16 bits 10- 32 bits 11 - 64 bits 0x2 22 reserved read only. 0x1 23 devloc 32-bit, 16-bit, or 8-bit device location. 0 - even bank 1 - odd bank 0x0 24 reserved read only. 0x0 25 latchfunct latch function in read cycles. 0 - always transparent 1 - latch enable signals are active. 0x0 27:26 reserved read only. 0x1 29:28 reserved read only. 0x1 30 parity parity support for the bank. 0- no parity support 1- parity supported 0x0 bits field name function initial value 30:0 various fields function as in device bank0. 0x146fffff
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 29 revision 1.1 galileo technology tm device bank2 parameters, offset: 0x464 device bank3 parameters, offset: 0x468 device boot bank parameters, offset: 0x46c in case of the boot bank, bits 23:20 are shown as ? because bits 21:20 are sampled at reset via dadr[11:10] to define the width of the boot device. 5.8 dma record each dma record includes four registers: byte count, source address, destination address, and a pointer to the next record. the record can be written by the cpu, pci, or dma controller in the process of fetching a new record from bits field name function initial value 30:0 various fields function as in device bank0. 0x146fffff bits field name function initial value 30:0 various fields function as in device bank0. 0x146fffff bits field name function initial value 30:0 various fields function as in device bank0. 0x14?fffff
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 30 revision 1.1 galileo technology tm memory. the structure of the record is illustrated in the following example: channel 0 dma byte count, offset: 0x800 channel 1 dma byte count, offset: 0x804 bits field name function initial value 15:0 bytect the number of bytes that are left in dma transfers. 0x0 bits field name function initial value 15:0 bytect the number of bytes that are left in dma transfers. 0x0 GT-64010A channel 0 dma registers byte count (bytect) source address (srcadd) destination address (destadd) next record pointer (nextrecptr): 0x10 0x10 bytect 0x14 srcadd 0x18 destadd 0x1c nextrecptr: 0x100 0x100 bytect 0x104 srcadd 0x108 destadd 0x10c nextrecptr: y xbytect xsrcadd x destadd x null pointer: 0x0 transfer #1 transfer #2 transfer #n
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 31 revision 1.1 galileo technology tm channel 2 dma byte count, offset: 0x808 channel 3 dma byte count, offset: 0x80c channel 0 dma source address, offset: 0x810 channel 1 dma source address, offset: 0x814 channel 2 dma source address, offset: 0x818 channel 3 dma source address, offset: 0x81c channel 0 dma destination address, offset: 0x820 channel 1 dma destination address, offset: 0x824 bits field name function initial value 15:0 bytect the number of bytes that are left in dma transfers. 0x0 bits field name function initial value 15:0 bytect the number of bytes that are left in dma transfers. 0x0 bits field name function initial value 31:0 srcadd the address that the dma controller w ill r ead the data from. 0x0 bits field name function initial value 31:0 srcadd the address that the dma controller w ill r ead the data from. 0x0 bits field name function initial value 31:0 srcadd the address that the dma controller w ill r ead the data from. 0x0 bits field name function initial value 31:0 srcadd the address that the dma controller w ill r ead the data from. 0x0 bits field name function initial value 31:0 destadd the address that the dma controller w ill write the data to. 0x0 bits field name function initial value 31:0 destadd the address that the dma controller w ill write the data to. 0x0
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 32 revision 1.1 galileo technology tm channel 2 dma destination address, offset: 0x828 channel 3 dma destination address, offset: 0x82c channel 0 next record pointer, offset: 0x830 channel 1 next record pointer, offset: 0x834 channel 2 next record pointer, offset: 0x838 channel 3 next record pointer, offset: 0x83c 5.9 dma channel control each dma channel has a control register to set its mode of operation independently of the other three channels. a channel can be programmed to transfer data through the GT-64010A. the dma reads data from the source address (pci, devices or dram) into an internal 32-byte fifo. from the internal fifo, the data is written to a destination address (pci as master, devices or dram) that can be independent from the source address. source addresses and destination addresses can be programmed to increment, decrement, or hold the same value throughout the dma transfer. for devices that can absorb a limited number of bytes at a time, the channel can be pro- grammed to limit the number of bytes transferred in each dma cycle. dma accesses can be initiated by an external source (demand mode) by asserting one of the four dmareq[3:0]* pins, or by an internal request (block mode) until the byte count reaches zero. all four channels have chaining support via linked lists of records. when the chaining mode is enabled, the dma con- troller will fetch the information (the record) for a new dma transfer directly out of memory (or a device or the pci) with- bits field name function initial value 31:0 destadd the address that the dma controller w ill write the data to. 0x0 bits field name function initial value 31:0 destadd the address that the dma controller w ill write the data to. 0x0 bits field name function initial value 31:0 nextrecptr the address for the next record of dma. a value of 0 means a null pointer (end of the chained list). 0x0 bits field name function initial value 31:0 nextrecptr the address for the next record of dma. a value of 0 means a null pointer (end of the chained list). 0x0 bits field name function initial value 31:0 nextrecptr the address for the next record of dma. a value of 0 means a null pointer (end of the chained list). 0x0 bits field name function initial value 31:0 nextrecptr the address for the next record of dma. a value of 0 means a null pointer (end of the chained list). 0x0
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 33 revision 1.1 galileo technology tm out involving the cpu. the location of the next record is in the next record pointer register (nextrecptr) and the dma controller will fetch records every dma transfer end until it reaches the null pointer (null pointer is zero). there are several mechanisms for status and control of the dma operations. an status interrupt can be programmed to be asserted every time the dma byte count reaches zero, or only when byte count reaches zero and the record is the last record in the chain (the nextrecptr is null). in addition, there is a status bit that indicates if a channel is active or not. a channel is active when it is enabled and its byte count is other than zero, or in chained mode when both its byte count is not equal to zero or its nextrecptr is not equal to null, or when it is disabled and its internal fifo is not empty. a channel can be controlled by disabling it temporarily, and a next record fetch can be forced through fet- nexrec in chained mode even if the current dma has not ended.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 34 revision 1.1 galileo technology tm channel 0 control, offset: 0x840 bits field name function initial value 0 reserved must be 0 0x0 1 reserved must be 0 0x0 3:2 srcdir source direction. 00 - increment source address 01 - decrement source address 10 - hold in the same value 0x0 5:4 destdir destination direction. 00 - increment destination address 01 - decrement destination address 10 - hold in the same value 0x0 8:6 dattranslim data transfer limit in each dma access. 101 - 1 byte 110 - 2 bytes 000 - 4 bytes 001 - 8 bytes 011 - 16 bytes 111 - 32 bytes 0x0 9 chainmod chained mode. 0 - chained mode; when a dma access is terminated, the parameters of the next dma access will come from a record in memory that a nextrecptr register points at. 1 - non-chained mode; only the values that are pro- grammed by the cpu (or pci) directly into the bytect, srcadd, and destadd registers are used. 0x0 10 intmode interrupt mode. 0 - interrupt asserted every time the dma byte count reaches terminal count. 1 - interrupt every null pointer (in chained mode) 0x0 11 transmod transfer mode. 0 - demand 1 - block 0x0 12 chanen channel enable. 0 - disable 1 - enable 0x0 13 fetnexrec fetch next record. 1 - forces a fetch of the next record (even if the cur- rent dma has not ended). this bit is reset after fetch is completed (meaningful only in chained mode). 0x0 14 dmaactst dma activity status (read only). 0 - channel is not active 1 - channel is active 0x0
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 35 revision 1.1 galileo technology tm channel 1 control, offset: 0x844 channel 2 control, offset: 0x848 channel 3 control, offset: 0x84c 5.10 additional notes on dma programming 5.10.1. non-chained mode in this mode, source, destination and byte count should be initialized prior to enabling the channel. chainmod should be set to 1. 5.10.2. chained mode all the channel records parameters for the current transaction (source, byte count, destination and next record pointer) should be initialized in memory devices or pci devices. the address of the first record should be initialized by writing it to the nextrecptr of the channel. the channel should be enabled via chanen=1, the fetnexrec should be set to 1 and the chainmod should be set to 0. 5.10.3. restarting a disabled channel in non-chained mode, chanen should be set to 1. in chained mode, the software should find out if the first fetch took place. if it did, only chanen should be set to 1. if it did not, the fetnexrec should also be set to 1. 5.10.4. reprogramming an active channel the channel should first be disabled via chanen=0. then it must be assured that the channel is no longer active (for example by polling the dmaactst of the channel). new dma parameters should be programmed prior to re-enabling the channel via chanen=1. 5.11 dma arbiter the dma controller has a programmable arbitration scheme between its four channels. the channels are grouped into two groups, one group includes channel 0 and 1, and the other group includes channels 2 and 3. the channels in each group can be programmed to have priority so that a selected channel has the higher priority, or to have the same prior- ity in round robin. the priority between the two groups can be programmed in a similar way so that a selected group has a higher priority, or to have the same priority in round robin. the priority scheme has additional flexib ility with the programmable priority option. with the priority option the dma bandwidth allocation can be divided in a fairer way. for example, if the prioopt bit is set to 0 and the priogrps field is set as 10, the requesting devices w ill get the dma in the order 0,1,2,0,1,3,0,1,2,0,1,3,..... (assuming that prioc han1/0 and priochan3/2 are set to round robin), while if the prioopt bit is set to 1 the requesting devices w ill get the dma in the order 0,1,0,1,0,1,2,3,2,3,2,3,..... the dma arbiter control register can be reprogrammed any time regardless of the channels status (active or not active). bits field name function initial value 14:0 various fields function as in channel 0 control. 0x0 bits field name function initial value 14:0 various fields function as in channel 0 control. 0x0 bits field name function initial value 14:0 various fields function as in channel 0 control. 0x0
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 36 revision 1.1 galileo technology tm some arbitration examples follow to facilitate the understanding of this register: 1. assuming all 4 channels are requested all the time, with arbiter control register = 0x40, the order will be: 0,2,1,3,0,2,1,3,..... with arbiter control register = 0x0, the order will be: 0,1,2,3,0,1,2,3,..... 2. assuming 3 channels are requested (0,1,2), with arbiter control register = 0x40, the order will be: 0,2,1,2,0,2,1,2,..... with arbiter control register = 0x0, the order will be: 0,1,2,0,1,2,0,1,2,..... 3. assuming all 4 channels are requested, with arbiter control register = 0x45, the order will be: 1,3,1,3,1,3,.....,0,2,0,2,0,2,...... with arbiter control register = 0x5, the order will be: 1,0,3,2,1,0,3,2,1,0,3,2,..... 4. assuming 3 channels are requested (0,1,2), with arbiter control register = 0x45, the order will be: 1,2,1,2,1,2,.....,0,0,0,0,0,0,..... with arbiter control register = 0x5, the order will be: 0,1,2,0,1,2,..... 5. assuming all 4 channels are requested, with arbiter control register = 0x55, the order will be: 3,3,3,3,3,3,2,2,2,2,2,1,1,1,1,0,0,0,...... with arbiter control register = 0x15, the order will be: 3,2,1,3,2,0,3,2,1,3,2,0,..... 6. assuming 3 channels are requested (0,1,2), with arbiter control register = 0x55, the order will be: 2,2,2,2,1,1,1,1,0,0,0,0,..... with arbiter control register = 0x15, the order will be: 2,1,2,0,2,1,2,0,..... 7. assuming 3 channels are requested (0,2,3), with arbiter control register = 0x55, the order will be: 3,3,3,...,2,2,2,...,0,0,0,..... with arbiter control register = 0x15, the order will be: 3,2,0,3,2,0,3,2,0,..... arbiter control, offset: 0x860 bits field name function initial value 1:0 priochan1/0 priority between channel 0 and channel 1. 00 - round robin 01 - priority to channel 1 over channel 0 10 - priority to channel 0 over channel 1 11 - reserved 0x0 3:2 priochan3/2 priority between channel 2 and channel 3. 00 - round robin 01 - priority to channel 3 over 2 10 - priority to channel 2 over 3 11 - reserved 0x0 5:4 priogrps priority between the group of channels 0/1 and the group of channels 2/3. 00 - round robin 01 - priority to channels 2/3 over 0/1 10 - priority to channels 0/1 over 2/3 11 - reserved 0x0 6 prioopt defines the arbiter behavior for high priority device. 0 - high priority device will reli nquish the bus for a requesting device for one dma transaction after it was serviced. 1 - high priority device will be granted as l ong as it requests the bus. 0x0
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 37 revision 1.1 galileo technology tm 5.12 timer / counter there are three 24-bit wide and one 32-bit wide timers/counters on the GT-64010A. each one can be selected to oper- ate as a timer or as a counter. in counter mode, the counter w ill c ount down to terminal count, w ill stop and issue an interrupt. in timer mode, it w ill c ount down, w ill issue an interrupt on terminal c ount, and w ill rel oad itself to the pro- grammed value and continue to count. reads from the counter or timer are done from the counter itself, while writes are to its register. for example, note that even though the registers are programmed to an initial value of 0 the counters w ill r ead 0xffff ff. in order to reprogram a timer/c ounter, it should first be disabled, then it should be loaded with a new value and after that it should be enabled as appropriate (counter or timer). timer/counter 0, offset: 0x850 timer/counter 1, offset: 0x854 timer/counter 2, offset: 0x858 timer/counter 3, offset: 0x85c bits field name function initial value 31:0 tc0value the counter or timer initial value. 0x0 bits field name function initial value 23:0 tc1value the counter or timer initial value. 0x0 bits field name function initial value 23:0 tc2value the counter or timer initial value. 0x0 bits field name function initial value 23:0 tc3value the counter or timer initial value. 0x0
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 38 revision 1.1 galileo technology tm timer/counter control, offset: 0x864 5.13 pci internal the pci internal registers include the following functions: byte swapping and clock ratios, timing for retries, dram and device bank sizes, interrupt acknowledge, system error masking, configuration address, and configuration data. bits field name function initial value 0 entc0 the timer/counter w ill c ount only when it is enabled. 0 - disable 1 - enable 0x0 1 seltc0 timer or counter selection. 0 - counter 1 - timer 0x0 2 entc1 the timer/counter w ill c ount only when it is enabled. 0 - disable 1 - enable 0x0 3 seltc1 timer or counter selection. 0 - counter 1 - timer 0x0 4 entc2 the timer/counter w ill c ount only when it is enabled. 0 - disable 1 - enable 0x0 5 seltc2 timer or counter selection . 0 - counter 1 - timer 0x0 6 entc3 the timer/counter w ill c ount only when it is enabled. 0 - disable 1 - enable 0x0 7 seltc3 timer or counter selection. 0 - counter 1 - timer 0x0
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 39 revision 1.1 galileo technology tm command, offset: 0xc00 time out & retry, offset: 0xc04 bits field name function initial value 0 byteswap when set to zero, the GT-64010A swaps the incoming and outgoing pci data. set to the same value sampled at reset into bit[12] of the cpu interface configura- tion register. 2:1 syncmode indicates the ratio between tclk and pclk as follows: 00 - when the pclk ranges from dc to 33mhz (default mode, works in all cases; use following set- tings for higher performance) 01 - when pclk is higher than half the tclk fre- quency (e.g. when tclk is 50mhz, syncmode can be set to 01 if the pci frequency is higher than 25 mhz). 1x - when the two clocks are synchronized (e.g. tclk = 50mhz, pclk = 25mhz) 0x0 bits field name function initial value 7:0 timeout0 specifies in pci clock units the number of clocks the GT-64010A, as a slave, holds the pci bus before the generation of retry termination. used for the first data transfer. 0x0f 15:8 timeout1 specifies in pci clock units the number of clocks the GT-64010A, as a slave, holds the pci bus before the generation of disconnect termination. used for data transfers following the first data.the number of pci clock cycles between the last trdy* rise and the stop* falling are n+1, where n is the timeout1 value. 0x07 23:16 retryctr specifies the number of retries of the GT-64010A master. the GT-64010A generates an interrupt when this timer expires. a value of 0x00 means retry for- ever. the number in retryctr does not include the first access of the transaction. 0x00
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 40 revision 1.1 galileo technology tm ras[1:0] bank size, offset: 0xc08 ras[3:2] bank size, offset: 0xc0c cs[2:0] bank size, offset: 0xc10 bits field name function initial value 31:12 banksize specifies the ras[1:0] address mapping in conjunc- tion with the ras[1:0] base address register. set to 0 indicates that the corresponding bit in the address and in the base address must be equal in order to have a hit. set to 1 indicates that the corre- sponding bit in the address is a dont-care. for example, bit 12 set to 1 indicates that the ras[1:0] size is 8kbytes (address bits [12:0] are changeable/dont-care). the set bits in the bank size must be sequential (e.g. 000 ...001, 000 ...011, 000...111 are correct values, whereas 000...010 and 000...100 are not). 0x00fff bits field name function initial value 31:12 banksize specifies the ras[3:2] address mapping in conjunc- tion with the ras[3:2] base address register. set to 0 indicates that the corresponding bit in the address and in the base address must be equal in order to have a hit. set to 1 indicates that the corre- sponding bit in the address is a dont-care. for example, bit 12 set to 1 indicates that the ras[3:2] size is 8kbytes (address bits [12:0] are changeable/dont-care). the set bits in the bank size must be sequential (e.g. 000 ...001, 000 ...011, 000...111 are correct values, whereas 000...010 and 000...100 are not). 0x00fff bits field name function initial value 31:12 banksize specifies the cs[2:0] address mapping in conjunction with the cs[2:0] base address register. set to 0 indicates that the corresponding bit in the address and in the base address must be equal in order to have a hit. set to 1 indicates that the corre- sponding bit in the address is a dont-care. for example, bit 12 set to 1 indicates that the cs[2:0] size is 8kbytes (address bits [12:0] are changeable/ dont-care). the set bits in the bank size must be sequential (e.g. 000 ...001, 000 ...011, 000...111 are correct values, whereas 000...010 and 000 ...100 are not). 0x01fff
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 41 revision 1.1 galileo technology tm cs[3] and boot cs bank size, offset: 0xc14 serr mask, offset: 0xc28 interrupt acknowledge, offset: 0xc34 bits field name function initial value 31:12 banksize specifies the cs[3] and boot cs address mapping in conjunction with the cs[3] and boot cs base address register. set to 0 indicates that the corresponding bit in the address and in the base address must be equal in order to have a hit. set to 1 indicates that the corre- sponding bit in the address is a dont-care. for example, bit 12 set to 1 indicates that the cs[3]/ boot cs size is 8kbytes (address bits [12:0] are changeable/dont-care). the set bits in the bank size must be sequential (e.g. 000 ...001, 000 ...011, 000...111 are correct values, whereas 000...010 and 000...100 are not). 0x00fff bits field name function initial value 0 addrerr mask bit. when set, serr* is asserted when the gt- 64010a detects a parity error on the address lines. 0x0 1 maswrerr mask bit. when set, serr* is asserted when the gt- 64010a detects a parity error during a master write operation. 0x0 2 masrderr mask bit. when set, serr* is asserted when the gt- 64010a detects a parity error during a master read operation. 0x0 3 memerr mask bit. when set, serr* is asserted when a memory parity error has been detected (applicable only when an external parity checking device is used). 0x0 4 masabort mask bit. when set, serr* is asserted when the gt- 64010a performs master abort. 0x0 5 tarabort mask bit. when set, serr* is asserted when the gt- 64010a detects a target abort. 0x0 bits field name function initial value 31:0 intack the data is meaningless. a cpu read operation to this register causes the GT-64010A to perform an interrupt acknowledge cycle on the pci bus. 0x00000000
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 42 revision 1.1 galileo technology tm configuration address, offset: 0xcf8 configuration data, offset: 0xcfc 5.14 interrupts intsum in the interrupt cause register is the logical or of bits[29:1], regardless of the mask registers values. this is in order to be notified via polling if any interrupt occurred within the GT-64010A. therefore, bit[0] of both the cpu mask and pci mask registers is read-only 0. cpuintsum in the interrupt cause register is the logical or of bits[29:26,20:1], masked by bits[29:26,20:1] of the cpu mask register. therefore, bits[25:21] of the cpu mask register, being non-relevant to interrupts directed to the cpu, are read-only 0. also bits[31:30], being summaries, are read-only 0. pciintsum in the interrupt cause register is the logical or of bits[25:1], masked by bits[25:1] of the pci mask register. therefore, bits[29:26] of the pci mask register, being non-relevant to interrupts directed to the pci, are read-only 0. also bits[31:30], being summaries, are read-only 0. bits field name function initial value 7:2 regnum indicates the register number. 0x00 10:8 functnum indicates the function type. 0x0 15:11 devnum indicates the device number. 0x00 23:16 busnum indicates the bus number. 0x00 31 configen when set, an access to the configuration data regis- ter is translated into a configuration or special cycle on the pci bus. 0x0 bits field name function initial value 31:0 config the data is transferred to/from the pci bus when the cpu accesses this register and the configen bit in the configuration address register is set. a cpu access to this register causes the GT-64010A to per- form a configuration or special cycle on the pci bus. 0x000
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 43 revision 1.1 galileo technology tm interrupt cause, offset: 0xc18 bits field name function initial value 0 intsum interrupt summary. logical or of all the interrupt bits, regardless of the mask registers values. 0x0 read only 1 memout asserts when the cpu accesses an address out of range in the memory decoding or a burst access to 8- /16-bit devices. 0x0 2 dmaout asserts when the dma accesses an address out of range. 0x0 3 cpuout asserts when the cpu accesses an address out of range. 0x0 4 dma0comp asserts at completion of dma channel 0 transfer. 0x0 5 dma1comp asserts at completion of dma channel 1 transfer. 0x0 6 dma2comp asserts at completion of dma channel 2 transfer. 0x0 7 dma3comp asserts at completion of dma channel 3 transfer. 0x0 8 t0exp asserts when timer 0 expires. 0x0 9 t1exp asserts when timer 1 expires. 0x0 10 t2exp asserts when timer 2 expires. 0x0 11 t3exp asserts when timer 3 expires. 0x0 12 masrderr asserts when the GT-64010A detects a parity error during a master read operation. 0x0 13 slvwrerr asserts when the GT-64010A detects a parity error during a slave write operation. 0x0 14 maswrerr asserts when the GT-64010A detects a parity error during a master write operation. 0x0 15 slvrderr asserts when the GT-64010A detects a parity error during a slave read operation. 0x0 16 addrerr asserts when the GT-64010A detects a parity error on the address lines. 0x0 17 memerr asserts when a memory parity error is detected. applicable only when an external parity checking device is used. 0x0 18 masabort asserts upon master abort. 0x0 19 tarabort asserts upon target abort. 0x0 20 retryctr asserts when the retry counter expires. 0x0 25:21 cpuint these bits are set by the cpu by writing 0 to gener- ate an interrupt on the pci bus. they are cleared when the pci writes 0. 0x0 29:26 pciint these bits are set by the pci by writing 0 to generate an interrupt on the cpu. they are cleared when the cpu writes 0. 0x0 30 cpuintsum interrupt summary. logical or of bits[29:26,20:1], masked by bits[29:26,20:1] of the cpu mask register. 0x0 31 pciintsum interrupt summary. logical or of bits[25:1], masked by bits[25:1] of the pci mask register. 0x0 all bits are cleared by writing a value of 0 by the cpu or pci, unless stated otherwise.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 44 revision 1.1 galileo technology tm cpu mask, offset: 0xc1c pci mask, offset: 0xc24 5.15 pci configuration the GT-64010A contains the required pci configuration registers. these registers are accessed from both the cpu and the pci. the GT-64010A translates cpu read and write cycles into configuration cycles using the pci configura- tion mechanism #1. mechanism #1 defines a way to translate the cpu cycles into both, pci configuration cycles on the pci and accesses to the GT-64010As internal configuration registers. the GT-64010A includes two registers: config- uration address (in offset 0xcf8) and configuration data (in offset 0xcfc). the general mechanism for accessing the configuration registers is to write a value into configuration address that specifies the pci bus, the device on that bus and the configuration register in that device being accessed. a read or write to configuration data w ill t hen causes the GT-64010A to translate that configuration address value to the requested cycle on the pci bus. if the busnum field in the configuration address register equals 0 but the devnum field is other than 0, a type0 access is done which addresses a device attached to the local pci bus (for devnum to idsel mapping, refer to the table following this para- graph). if the busnum field in the configuration address register is other than 0, a type1 access is done which addresses a device attached to a remote pci bus. the cpu accesses the GT-64010As internal configuration registers when the fields devnum and busnum in the configuration address register are equal to 0. the GT-64010A configu- ration registers are also accessed from the pci using the normal pci read and write configuration cycles. note: the cpu interface unit cannot distinguish between an access to the GT-64010A pci configuration space and an access to some other pci device configuration space. this is because both are accessed using an access to the gt- 64010a internal space (i.e. configuration data register). when the cpu is operating in big endian mode, any access to the GT-64010A internal space undergoes byte swapping as all internal registers are little endian. with the cpu operat- ing in big endian mode and the pci byteswap bit (bit [0] @ 0xc00) set to 0 (i.e., swap bytes), bytes w ill be sw apped once for pci configuration accesses intended for the GT-64010A configuration space but w ill be sw apped twice for pci configuration accesses intended for devices external to the GT-64010A. this requires the software to format write data and interpret read data differently for pci configuration accesses to the GT-64010A and configuration accesses through the GT-64010A. see also appendix 11.1. bits field name function initial value 31:0 cpumask mask to the cpu interrupt line for the appropriate bits in the interrupt cause register. bits 0, 25:21, 31:30 are read-only 0. 0x00000000 bits field name function initial value 31:0 pcimask mask to the pci interrupt line for the appropriate bits in the interrupt cause register. bits 0, 31:26 are read- only 0. 0x00000000
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 45 revision 1.1 galileo technology tm devnum to idsel mapping a special cycle is generated whenever the configuration data register is written to while the configuration address register has been previously written with 0 for busnum, 1f for devnum, 7 for functnum and 0 for regnum. an interrupt acknowledge cycle is generated whenever the interrupt acknowledge (0xc34) register is read. device and vendor id, offset: 0x000 devnum[15:11] pad[31:11] 00001 0 0000 0000 0000 0000 0001 00010 0 0000 0000 0000 0000 0010 00011 0 0000 0000 0000 0000 0100 00100 0 0000 0000 0000 0000 1000 - - - - - - 10101 1 0000 0000 0000 0000 0000 00000, 10110 - 11111 0 0000 0000 0000 0000 0000 bits field name function initial value 31:16 devid provides the unique GT-64010A id number (0x146). 0x0146 15:0 venid provides the manufacturer of the GT-64010A (0x11ab). 0x11ab
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 46 revision 1.1 galileo technology tm status and command, offset: 0x004 class code and revision id, offset: 0x008 bits field name function initial value 0 ioen controls the GT-64010As response to i/o accesses. 0 - disable 1 - enable 0x0 1 memen controls the GT-64010As response to memory accesses. 0 - disable 1 - enable 0x0 2 masen controls the GT-64010As ab ility to act as a master on the pci bus. 0 - disable 1 - enable 0x0 4 memwrinv controls the GT-64010As ab ility to generate memory write & invalidate command on the pci bus. 0 - disable 1 - enable 0x0 6 perren controls the GT-64010As ab ility to res pond to parity errors on the pci by asserting the perr* pin. 0 - disable 1 - enable 0x0 8 serren controls the GT-64010As ab ility to assert the serr* pin. 0 - disable 1 - enable 0x0 23 tarfastbb read only bit. indicates that the GT-64010A is capa- ble of accepting fast back-to-back transactions on the pci bus. 0x1 24 datapardet this bit is set by the GT-64010A when it detects a data parity error during master operation. 0x0 27:25 devseltim these pins indicate the GT-64010A s devsel timing (medium), per the pci standard. 0x1 read only 28 tarabort this bit is set upon target abort. 0x0 29 masabort this pin is set upon master abort. 0x0 30 syserr this pin is set upon system error. 0x0 31 detparerr this pin is set upon detection of parity error (in both, master and slave operations). 0x0 bits field name function initial value 7:0 revid indicates the GT-64010A revision number. 0x02 31:24 baseclass indicates the GT-64010A base class (0x6 - bridge device). 0x06 23:16 subclass indicates the GT-64010A subclass (0x0 - host bridge). 0x00
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 47 revision 1.1 galileo technology tm header type, latency timer, cache line, offset: 0x00c for more information on these fields, please refer to the pci specification. access of pci masters to dram banks, devices and internal space is achieved once there is a match between the address presented over the pci bus and the space defined by the respective base/size register pair. the GT-64010A incorporates three swapped base address registers for ras[1:0], ras[3:2] and cs[3] & bootcs. when the address matches a swapped base address register (and of course should not match its respective non-swap base address register), the data transferred will undergo the opposite to what is indicated by the byteswap bit (bit[0] of 0xc00). e.g. using this mechanism, one could write data directly to dram and read it byte-swapped without cpu processing. the size registers could not define a zero size space. in order to enable the system designer to use addresses which are within a certain space without having the GT-64010A respond to these addresses, a base address enable register is incorporated. a disabled space will not tri gger device response should the address fall within the space defined by its base/size register pair. ras[1:0] base address, offset: 0x010 ras[1:0] swapped base address, offset: 0x028 ras[3:2] base address, offset: 0x014 ras[3:2] swapped base address, offset: 0x02c bits field name function initial value 7:0 cacheline specifies the GT-64010As cache line size (size=8). 0x07 15:8 lattimer specifies in units of pci bus clocks the value of the latency timer of the GT-64010A. 0x00 23:16 headtype specifies the layout of bytes 10h through 3fh. 0x00 bits field name function initial value 31:12 base defines the address assignment of ras[1:0] (see ras[1:0] bank size). 0x00000 bits field name function initial value 31:12 base defines the address assignment of swapped ras[1:0] (see ras[1:0] bank size). 0x00000 bits field name function initial value 31:12 base defines the address assignment of ras[3:2] (see ras[3:2] bank size). 0x01000 bits field name function initial value 31:12 base defines the address assignment of swapped ras[3:2] (see ras[3:2] bank size). 0x01000
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 48 revision 1.1 galileo technology tm cs[2:0] base address, offset: 0x018 cs[3] and boot cs base address, offset: 0x01c cs[3] and boot cs swapped base address, offset: 0x030 internal registers memory mapped base address, offset: 0x020 internal registers i/o mapped base address, offset: 0x024 bits field name function initial value 31:12 base defines the address assignment of cs[2:0] (see cs[2:0] bank size). 0x1c000 bits field name function initial value 31:12 base defines the address assignment of cs[3] and boot cs (see cs[3] and boot cs bank size). 0x1f000 bits field name function initial value 31:12 base defines the address assignment of swapped cs[3] and boot cs (see cs[3] and boot cs bank size). 0x1f000 bits field name function initial value 31:12 memmapbase defines the address assignment of the GT-64010As internal registers. 0x14000 bits field name function initial value 31:12 iomapbase defines the address assignment of the GT-64010As internal registers. 0x14000
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 49 revision 1.1 galileo technology tm base address registers enable, offset: 0x034 interrupt pin and line, offset: 0x03c for more information on these fields, please refer to the pci specification. bits field name function initial value 8 ras[1:0]en controls address matching with ras[1:0] base/size. 1 - disable 0 - enable 0x0 7 ras[3:2]en controls address matching with ras[3:2] base/size. 1 - disable 0 - enable 0x0 6 cs[2:0]en controls address matching with cs[2:0] base/size. 1 - disable 0 - enable 0x0 5 cs[3] & boot csen controls address matching with cs[3] & boot cs base/size. 1 - disable 0 - enable 0x0 4 intmemen controls address matching with internal registers- memory mapped base/size. 1 - disable 0 - enable 0x0 3 intioen controls address matching with internal registers i/o mapped base/size. 1 - disable 0 - enable 0x0 2 swras[1:0]en controls address matching with swapped ras[1:0] base/size. 1 - disable 0 - enable 0x1 1 swras[3:2]en controls address matching with swapped ras[3:2] base/size. 1 - disable 0 - enable 0x1 0 swcs[3] & boot csen controls address matching with swapped cs[3] & boot cs base/size. 1 - disable 0 - enable 0x1 bits field name function initial value 7:0 intline provides interrupt line routing information. 0x00 15:8 intpin indicates which interrupt pin is used by the gt- 64010a. the GT-64010A uses inta. 0x01
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 50 revision 1.1 galileo technology tm 6. restrictions 6.1 cpu interface a) the cpu should not attempt an access before 10 tclk cycles following deassertion of rst* have expired. b) cacheopmap should not be written to a value other than 0 unless cachepres bit is set (see section 3.2). c) the cpu interface supports only dddd and dxdxdxdx write patterns. d) a pci i/o read intended for synchronization barrier should not be more than one long word (4 bytes). any pci i/o read of more than 4 bytes w ill be carried out wit hout checking the internal fifos. e) a write of more than 4 bytes to internal space w ill be i gnored. a read of more than 4 bytes to internal space will result in transaction termination with bus-error indication (syscmd[5] equal 1). 6.2 memory interface a) if latches are not present, all banks must be programmed to be on the even bus. programming the registers to 64- bit mode or to dynamically controlled latches w ill result in an error. b) unless the boot device is 64-bits wide, the boot w ill be on the even bank. c) all device parameters (section 3.7) must be greater or equal to 3. i.e., acctofirst, acctonext, adstowr, wractive and wrhigh. d) when working with an 8- or 16-bit bus from cpu, a read/write operation can not exceed 64-bits (8 bytes). e) when working with an 8- or 16-bit bus from dma/pci, a read/write operation cant exceed 32-bits (4 bytes). f) when an erroneous address is issued or a burst operation is performed to an 8- or 16-bit device, the GT-64010A forces an interrupt (unless masked). if a sequence of address misses occurs, there w ill be no other interrupt prior to resetting the appropriate bit in the cause register and no new address w ill be registered in the address decode error register (0x470) prior to reading it. g) when the cpu reads from an address which is decoded in the cpu interface unit as being a hit for cs[2:0]* or cs[4:3]* and decoded as a miss in the dram/device interface unit, the cycle w ill complete only if r eady* is asserted (i.e., driven low). although being a result of improper and inconsistent programming of the address space defining registers, the following 2 workarounds exist: ? ready* should always be asserted (low) when cstiming* is inactive (high). ? if the ready* signal is not needed in the system, the dmareq[0]/ready* pin should either be programmed as ready* and constantly driven active (low) or be programmed as dmareq[0]*. 6.3 pci interface note: no pci access should be attempted before 6 pclk cycles following deassertion of rst* have expired. 6.3.1. master a) latency count, as specified in lattimer (section 3.14), should not be programmed to less than 6. 6.3.2. slave a) the set bits in the bank size registers must be sequential. b) when the slave is locked, in order to prevent a deadlock, all transactions to internal registers (i/o or memory cycles) are not supported (retry w ill be iss ued). 6.4 dma a) transfers of less than 4 bytes are not supported. b) in order to restart a channel after it has been enabled, it should first be checked that the dmaactst bit is set to not active (see section 3.9). c) when source or destination address is decremented, both addresses should be word-aligned (that is, a1 and a0 should be both zero), and byte count should be a multiple of 4 (this applies for burst limits greater than 4 bytes). d) when burst limit is less than or equal to 4 bytes, no support in decrement.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 51 revision 1.1 galileo technology tm e) when using the address hold option in the source direction (srcdir in section 3.9), the source address should keep the following rules: ? word-aligned if burst limit is greater or equal to 4 bytes. ? bits [1:0] equal to 00, 01 or 10 if burst limit is equal to 2 bytes. ? no restriction for burst limit equal to 1 byte. f) when using the address hold option in the destination direction (destdir in section 3.9), the following rules should be kept: ? both source and destination addresses should be word-aligned if burst limit is greater or equal to 4 bytes. ? bit [0] of both source and destination addresses should be equal to 0 if burst limit is equal to 2 bytes. ? no restriction for burst limit equal to 1 byte. ? fly-by is not supported. g) records addresses should be a multiple of 16.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 52 revision 1.1 galileo technology tm 7. pinout table 7.1 256 pin pqfp (sorted by number) pin # signal name pin # signal name pin # signal name 1 vdd 36 pad[15] 71 syscmd[2] 2 vss 37 vss 72 syscmd[1] 3 pad[27] 38 pad[14] 73 syscmd[0] 4 pad[26] 39 vss 74 sysad[0] 5 pad[25] 40 pad[13] 75 sysad[1] 6 pad[24] 41 pad[12] 76 sysad[2] 7 cbe[3]* 42 pad[11] 77 sysad[3] 8 idsel 43 pad[10] 78 sysad[4] 9 vdd 44 pad[9] 79 sysad[5] 10 vss 45 vdd 80 vss 11 pad[23] 46 vss 81 vdd 12 pad[22] 47 pad[8] 82 sysad[6] 13 pad[21] 48 cbe[0]* 83 sysad[7] 14 pad[20] 49 pad[7] 84 sysad[8] 15 pad[19] 50 pad[6] 85 sysad[9] 16 vss 51 pad[5] 86 sysad[10] 17 pad[18] 52 vdd 87 sysad[11] 18 pad[17] 53 vss 88 sysad[12] 19 pad[16] 54 pad[4] 89 sysad[13] 20 cbe[2]* 55 pad[3] 90 vss 21 frame* 56 pad[2] 91 tclk 22 vdd 57 pad[1] 92 vdd 23 vss 58 pad[0] 93 sysad[14] 24 irdy* 59 oe64* 94 sysad[15] 25 trdy* 60 hit/dmareq[3]* 95 sysad[16] 26 devsel* 61 interrupt* 96 sysad[17] 27 stop* 62 vss 97 sysad[18] 28 vdd 63 syscmd[8] 98 vss 29 lock* 64 syscmd[7] 99 vdd 30 perr* 65 syscmd[6] 100 sysad[19] 31 vdd 66 syscmd[5] 101 vss 32 vss 67 syscmd[4] 102 sysad[20] 33 serr* 68 vss 103 sysad[21] 34 par 69 vdd 104 sysad[22]
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 53 revision 1.1 galileo technology tm 35 cbe[1]* 70 syscmd[3] 105 sysad[23] 106 sysad[24] 144 sysad[53] 182 ad[21] 107 sysad[25] 145 sysad[54] 183 ad[20] 108 sysad[26] 146 sysad[55] 184 ad[19] 109 sysad[27] 147 sysad[56] 185 ad[18] 110 sysad[28] 148 vss 186 ad[17] 111 vss 149 sysad[57] 187 ad[16] 112 vdd 150 sysad[58] 188 ad[15] 113 sysad[29] 151 sysad[59] 189 ad[14] 114 sysad[30] 152 sysad[60] 190 ad[13] 115 sysad[31] 153 sysad[61] 191 vss 116 sysad[32] 154 sysad[62] 192 ad[12] 117 validout* 155 sysad[63] 193 ad[11] 118 validin* 156 dmareq[0]*/ready* 194 ad[10] 119 wrrdy* 157 dmareq[1]*/parerr* 195 ad[9] 120 release* 158 leadre/dmareq[2]* 196 ad[8] 121 sysad[33] 159 leadro 197 ad[7] 122 sysad[34] 160 vdd 198 ad[6] 123 sysad[35] 161 vss 199 ad[5] 124 sysad[36] 162 oeb 200 ad[4] 125 vss 163 oee* 201 ad[3] 126 sysad[37] 164 oeo* 202 vss 127 sysad[38] 165 lee 203 ad[2] 128 sysad[39] 166 leo 204 ad[1]/devrw* 129 sysad[40] 167 ale 205 ad[0]/bootcs* 130 sysad[41] 168 vss 206 dwr* 131 sysad[42] 169 cstiming* 207 ecas[3]* 132 sysad[43] 170 ad[31]/cs[3]* 208 ecas[2]* 133 sysad[44] 171 ad[30]/cs[2]* 209 ecas[1]* 134 sysad[45] 172 ad[29]/cs[1]* 210 ecas[0]* 135 sysad[46] 173 ad[28]/cs[0]* 211 vdd 136 vss 174 ad[27]/dmaack[3]* 212 vss pin # signal name pin # signal name pin # signal name
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 54 revision 1.1 galileo technology tm 7.2 5.2 256-ball bga + 16-ball ground matrix pinout (sorted by numbers) note: 272 balls altogether, 256-ball periphery balls in a 4-row array, plus 16-ball ground matrix in the center. 137 vdd 175 ad[26]/dmaack[2]* 213 ocas[3]* 138 sysad[47] 176 ad[25]/dmaack[1]* 214 ocas[2]* 139 sysad[48] 177 ad[24]/dmaack[0]* 215 ocas[1]* 140 sysad[49] 178 ad[23] 216 ocas[0]* 141 sysad[50] 179 ad[22] 217 ras[3]* 142 sysad[51] 180 vss 218 ras[2]* 143 sysad[52] 181 vdd 219 ras[1]* 220 ras[0]* 233 dadr[5]/ewr[2]* 246 vdd 221 vss 234 dadr[4]/ewr[1]* 247 pclk 222 vdd 235 dadr[3]/ewr[0]* 248 vss 223 dadr[11]/ads* 236 dadr[2]/badr[2] 249 gnt* 224 vdd 237 dadr[1]/badr[1] 250 req* 225 vss 238 dadr[0]/badr[0] 251 vss 226 dadr[10]/owr[3]* 239 jtrst* 252 vdd 227 dadr[9]/owr[2]* 240 jtdi 253 pad[31] 228 dadr[8]/owr[1]* 241 jtms 254 pad[30] 229 dadr[7]/owr[0]* 242 jtdo 255 pad[29] 230 dadr[6]/ewr[3]* 243 jtclk 256 pad[28] 231 vss 244 int* 232 vdd 245 rst* ball # signal name ball # signal name ball # signal name a1 ad[13] b16 sysad[52] d11 vdd a2 ad[14] b17 sysad[49] d12 vss a3 ad[16] b18 sysad[46] d13 vss a4 ad[19] b19 sysad[43] d14 vdd a5 ad[22] b20 sysad[41] d15 vdd a6 ad[25]/dmaack[1]* c1 ad[10] d16 vss a7 ad[28]/cs[0]* c2 ad[9] d17 vss a8 ad[31]/cs[3]* c3 ad[17] d18 sysad[36] a9 leo c4 ad[20] d19 sysad[37] a10 oee* c5 ad[23] d20 sysad[35] a11 leadre/dmareq[2]* c6 ad[26]/dmaack[2]* e1 ad[4] pin # signal name pin # signal name pin # signal name
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 55 revision 1.1 galileo technology tm a12 sysad[63] c7 ad[29]/cs[1]* e2 ad[3] a13 sysad[60] c8 cstiming* e3 ad[5] a14 sysad[57] c9 lee e4 vss a15 sysad[54] c10 oeb e17 vss a16 sysad[51] c11 dmareq[1]*/parerr* e18 wrrdy* a17 sysad[48] c12 sysad[62] e19 sysad[34] a18 sysad[45] c13 sysad[59] e20 release* a19 sysad[42] c14 sysad[56] f1 ad[1]/devrw* a20 sysad[40] c15 sysad[53] f2 ad[0]/bootcs* b1 ad[12] c16 sysad[50] f3 ad[2] b2 ad[11] c17 sysad[47] f4 vdd b3 ad[15] c18 sysad[44] f17 sysad[33] b4 ad[18] c19 sysad[39] f18 sysad[32] b5 ad[21] c20 sysad[38] f19 validin* b6 ad[24]/dmaack[0]* d1 ad[7] f20 validout* b7 ad[27]/dmaack[3]* d2 ad[6] g1 ecas[3]* b8 ad[30]/cs[2]* d3 ad[8] g2 ecas[2]* b9 ale d4 vss g3 dwr* b10 oeo* d5 vss g4 vdd b11 leadro d6 vdd g17 vdd b12 dmareq[0]*/ready* d7 vdd g18 sysad[28] b13 sysad[61] d8 vss g19 sysad[31] b14 sysad[58] d9 vss g20 sysad[30] b15 sysad[55] d10 vdd h1 ecas[0]* h2 ocas[3]* l12 vss r18 sysad[2] h3 ecas[1]* l17 sysad[14] r19 sysad[4] h4 vss l18 sysad[15] r20 sysad[3] h17 sysad[29] l19 sysad[17] t1 jtrst* h18 sysad[25] l20 sysad[16] t2 jtms h19 sysad[27] m1 dadr[9]/owr[2]* t3 jtdi h20 sysad[26] m2 dadr[11]/ads* t4 vss j1 ocas[1]* m3 dadr[10]/owr[3]* t17 vss j2 ocas[0]* m4 vss t18 syscmd[0] j3 ocas[2]* m9 vss t19 sysad[1] j4 vss m10 vss t20 sysad[0] j9 vss m11 vss u1 jtdo j10 vss m12 vss u2 jtclk j11 vss m17 vss u3 vss ball # signal name ball # signal name ball # signal name
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 56 revision 1.1 galileo technology tm j12 vss m18 sysad[12] u4 vss j17 vss m19 sysad[13] u5 vss j18 sysad[22] m20 tclk u6 vdd j19 sysad[24] n1 dadr[7]/owr[0]* u7 vdd j20 sysad[23] n2 dadr[8]/owr[1]* u8 vss k1 ras[3]* n3 dadr[6]/ewr[3]* u9 vss k2 ras[2]* n4 vss u10 vdd k3 vdd n17 sysad[6] u11 vdd k4 vdd n18 sysad[9] u12 vss k9 vss n19 sysad[11] u13 vss k10 vss n20 sysad[10] u14 vdd k11 vss p1 dadr[3]/ewr[0]* u15 vdd k12 vss p2 dadr[5]/ewr[2]* u16 vss k17 sysad[18] p3 dadr[4]/ewr[1]* u17 vss k18 sysad[19] p4 vdd u18 syscmd[3] k19 sysad[21] p17 vdd u19 syscmd[1] k20 sysad[20] p18 sysad[5] u20 syscmd[2] l1 ras[1]* p19 sysad[8] v1 int* l2 ras[0]* p20 sysad[7] v2 pclk l3 vdd r1 dadr[1]/badr[1] v3 pad[31] l4 vdd r2 dadr[2]/badr[2] v4 pad[28] l9 vss r3 dadr[0]/badr[0] v5 pad[25] l10 vss r4 vdd v6 idsel l11 vss r17 vdd v7 pad[21] v8 pad[18] w6 pad[22] y4 pad[27] v9 cbe[2]* w7 pad[19] y5 pad[24] v10 trdy* w8 pad[16] y6 pad[23] v11 lock* w9 irdy* y7 pad[20] v12 par w10 stop* y8 pad[17] v13 pad[14] w11 serr* y9 frame* v14 pad[11] w12 pad[15] y10 devsel* v15 pad[8] w13 pad[12] y11 perr* v16 pad[6] w14 pad[9] y12 cbe[1]* v17 pad[3] w15 pad[7] y13 pad[13] v18 pad[0] w16 pad[4] y14 pad[10] v19 syscmd[4] w17 pad[1] y15 cbe[0]* v20 syscmd[5] w18 hit/dmareq[3]* y16 pad[5] w1 rst* w19 syscmd[8] y17 pad[2] ball # signal name ball # signal name ball # signal name
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 57 revision 1.1 galileo technology tm w2 req* w20 syscmd[6] y18 oe64* w3 pad[29] y1 vss y19 interrupt* w4 pad[26] y2 gnt* y20 syscmd[7] w5 cbe[3]* y3 pad[30] ball # signal name ball # signal name ball # signal name j9 m12 m9 j12 a1 y1 y20 a20 ball sequence top view 16-ball ground matrix
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 58 revision 1.1 galileo technology tm 8. dc characteristics - preliminary/subject to change 8.1 absolute maximum ratings 8.2 recommended operating conditions 8.3 dc electrical characteristics over operating range (tc=0-70 o c; vdd=+5v, +/-5%) symbol parameter min. max. unit vdd supply voltage -0.3 6.5 v vi input voltage -0.3 vdd+0.3 v vo output voltage -0.3 vdd+0.3 v io output current 24 ma iik input protect diode current +-20 ma iok output protect diode current +-20 ma top operating temperature 0 85 oc tstg storage temperature -40 125 oc esd 2000 v symbol parameter min. typ. max. unit vdd supply voltage 4.75 5.25 v vi input voltage 0 vdd v vo output voltage 0 vdd v top operating temperature 0 70 oc cin input capacitance 7.2 pf cout output capacitance 7.2 pf symbol parameter test condition min. typ. max. unit vih input high level guaranteed logic high level 2.0 vdd + 0.5v v vil input low level guaranteed logic low level -0.5 0.8 v voh output high voltage ioh = 2 ma ioh = 4 ma ioh = 8 ma ioh = 12 ma ioh = 16 ma ioh = 24 ma 2.4 v
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 59 revision 1.1 galileo technology tm note: pullup/pulldown resistors are 45kohm minimum, 65kohm typical, 80kohm maximum. 8.4 package thermal characteristics 256pqfp package 8.5 package thermal characteristics 272 bga package vol output low voltage iol = 2 ma iol = 4 ma iol = 8 ma iol = 12 ma iol = 16 ma iol = 24 ma 0.4 v iih input high current +-1 ua iil input low current +-1 ua iozh high impedance output current +-1 ua iozl high impedance output current +-1 ua vh input hysteresis vdd = 4.5v vdd = 5.0v vdd = 5.5v 0.52 0.54 0.56 0.60 0.61 0.62 mv icc operating current 400 ma symbol max. unit q jc 12 c/w q ja 35 c/w symbol max. unit q jc 9.6 c/w q ja 22 c/w symbol parameter test condition min. typ. max. unit
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 60 revision 1.1 galileo technology tm 9. ac timing - preliminary/subject to change (tc= 0-70 o c; vdd= +5v, +/- 5%) symbol signals description min max unit t1 tclk pulse width high 8 ns t2 tclk pulse width low 8 ns t3 tclk clock period 20 30 ns t4 tclk rise time 3 ns t5 tclk fall time 3 ns t6 rst* active 10 tclk t7 hit/dmareq[3]*, leadre/dmareq[2]*, dmareq[1]*/parerr*, ad[31:0] setup 5 ns t8 dmareq[0]*/ready*, setup 11 ns t9 wrrdy*, validin*, oe64* syscmd[8:0], interrupt* delay 2 12 ns t10 dadr[11:0] delay (row address) 3 18 ns t11 dadr[11:0] delay (column address) 3 11 ns t12 badr[2:0], ads*, sysad[63:0] delay 2 13 ns t13 ewr[3:0]*, owr[3:0]* delay from tclk falling edge 2 13 ns t14 dwr*, cstiming*, ale, delay 2 10 ns t15 ecas[3:0]*, ocas[3:0]*, oeb, oeo*, oee*, ad[31:0] delay 29ns t16 ale, leo, lee delay from tclk falling edge 2 10 ns t17 validout*, release*, hit/dmareq[3]*, leadre/dmareq[2]*, dmareq[1]*/parerr*, sysad[63:0], syscmd[8:0], ad[31:0], dmareq[0]*/ready* hold 1 ns t18 validout*, release*,sysad[63:0], syscmd[8:0] setup 3 ns t19 leadre/dmareq[2]*, leadro delay 2 10 ns t20 leadre/dmareq[2]*, leadro delay from tclk falling edge 2 10 ns t21 leo, lee delay 2 9 ns t22 ras[3:0]* delay 3 8 ns
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 61 revision 1.1 galileo technology tm notes: 1. all delays, setup, and hold times are referred to tclk rising edge, unless stated otherwise. 2. all outputs are specified for 50pf load except: wrrdy*, validin*, ale, leadro, leadre/dmareq[2]* - 30pf, inter- rupt* - 20 pf. 3. tclk frequency must be equal or greater than pclk frequency. 4. maximum allowable tclk to pclk skew in sync. mode is 2ns. symbol signals description min max unit pclk, frame*, irdy*, trdy*, devsel*, stop*, perr*, par, pad[31:0], cbe[3:0]*, gnt*, idsel, lock*, req*, serr*, int* see pci specification rev. 2.1. referred to pclk. all inputs including jtrst*, jtdi, jtms setup to jtclk 12 ns all inputs including jtrst*, jtdi, jtms hold from jtclk 1 ns all outputs delay from jtclk float to valid delay drive to float delay 2 2 2 10 15 15 ns jtdo delay from jtclk falling 2 10 ns
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 62 revision 1.1 galileo technology tm t6 0ns 100ns 200ns rst* tclk reset t4 t5 t1 t2 t3 tclk 0ns 50ns tclk
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 63 revision 1.1 galileo technology tm t22 f0f0f0f0f 001 801 800 803 802 001 f0f0f0f0f fd f cpu burst read from 64-bit standard dram (cas low 2 cycles) 0ns 100ns 200ns 300ns 400ns tclk validout* release* syscmd sysad validin* wrrdy* ras* ecas* ocas* dwr* dadr ad cstiming* lee leo oee* oeo* oeb oe 64* le adro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 64 revision 1.1 galileo technology tm t9 t10 t11 f0f0f0f0f 000 001 000 003 002 001 f0f0f0f0f fe f cpu burst read from 64-bit standard dram (fastest ras & cas) 0ns 50ns 100ns 150ns 200ns 250ns 300ns tclk validout* release* syscmd sysad validin* wrrdy* ras* ecas* ocas* dwr* dadr ad cstiming* lee leo oee* oeo* oeb oe64* leadro t1 5
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 65 revision 1.1 galileo technology tm t1 7 f0f0f0f0f 001 000 003 001 f0f0f0f0f fe f cpu burst write to 64-bit standard dram (fastest ras & cas) 002 aaa 0ns 100ns 200ns 300ns 40 tclk validout* release* syscmd sysad validin* wrrdy* ras* ecas* oca s* dwr* dadr ad cstiming* le e le o oee* oe o* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 66 revision 1.1 galileo technology tm 018 110 f 0f a aa 002 000 001 002 f 0f fef cpu byte read from 64-bit standard dram (fastest ras & cas) 55555555 0ns 50ns 100ns 150ns 20 tclk validout* release* syscmd sysad validin* wrrdy* ras* ecas* ocas* dwr* dadr ad cstiming* lee leo oee* oeo* oe b oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 67 revision 1.1 galileo technology tm f 002 f cf fe cpu 2 bytes write to 64-bit standard dram (fastest ras & cas) f 009 000 001 2d2 0ns 50ns 100ns 150ns 200ns tclk validout* release* syscmd sysad validin* wrrdy* ras* ecas* ocas* dwr* dadr ad cstiming* lee leo oee* oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 68 revision 1.1 galileo technology tm 6c f ef f 0f 000 001 000 001 000 pci 2 bytes read from standard dram 0ns 100ns 200ns 300ns 400ns pclk req* gnt* frame* pad cb e* par devsel* irdy* trdy* lock* tclk ra s* ecas* ocas* dw r* dadr ad cstiming* lee leo oee* oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 69 revision 1.1 galileo technology tm c0 fef f 000 e f f f f f 000 000 pci 32 bytes read multiple from dram 0ns 250ns 500ns 750ns pclk req* gnt* frame* pad cbe* par devsel* irdy* trdy* lock* tclk ras* ecas* ocas* dwr* dadr ad cstiming* lee leo oee * oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 70 revision 1.1 galileo technology tm 7e f ef f 000 f ef 001 002 000 pci byte write to dram 0ns 100ns 200ns 300ns 400ns pclk req* gnt* frame* pad cbe* par devsel* ir dy* trdy* lock* tclk ras* ecas* ocas* dw r* dadr ad cstiming* lee leo oee* oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 71 revision 1.1 galileo technology tm 70 f f 000 f 000 ef pci 32 bytes write to dram 0ns 250ns 500ns 750ns pclk req* gnt* frame* pad cbe* par devsel* ir dy* trdy* lock* tclk ras* ecas* ocas* dw r* dadr ad cstiming* lee leo oee* oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 72 revision 1.1 galileo technology tm t1 6 t12 t13 t14 a0 2 12 06421 0 f 50 0 f cpu burst read from device (acctofirst =4, acctonext=2) 0ns 100ns 200ns 300ns 400ns tclk validout* release* syscmd sysad validin* wrrdy* ale ads* ad badr ewr* owr* cstiming* lee leo oee * oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 73 revision 1.1 galileo technology tm t18 t19 t20 0f e0000017 12 06 4 f 0 0f 0 0 1c0 aaaaaaaa 2 f0 f 0 f 0 5 f0f0 f f 5 cpu burst write to 64-bit device (adstowr=3, wractive=2, wrhigh=1) 0ns 100ns 200ns 300ns 400ns 500ns tclk validout* release* syscmd sysad validin* wrrdy* ale ads* ad badr ewr* owr* cstiming* le e leo oee* oeo* oeb oe64* leadro t21
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 74 revision 1.1 galileo technology tm 51 20 50 e 1 f f 2 5 5 0f f cpu 5 bytes write to 64-bit device (adstowr=3, wractive=2, wrhigh=1) 0ns 100ns 200ns 300ns 400ns tclk validout* release* syscmd sysad validin* wrrdy* al e ads* ad badr ewr* owr* cstiming* ready* lee leo oee* oeo* oeb oe64* leadro t8
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 75 revision 1.1 galileo technology tm 50 20 50 f f 2 0 0 cpu 3 bytes read from 64-bit device (adstowr=3, wractive=2, wrhigh=1) 0ns 50ns 100ns 150ns 200ns 250ns tcl k validout* release* syscmd sysad validin* wrrdy* ale ads* ad badr ewr* owr* cstiming* lee leo oee* oeo* oeb oe64* lea dro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 76 revision 1.1 galileo technology tm f 0f0f0f0 f 002 001 000 001 002 003 f0f0f0f0f fb f cpu burst read from 32-bit dram (fastest ras & cas) 0 0 0 0 0 0 0 0 f f f f f f f f 004 005 006 007 000 001 0ns 100ns 200ns 300ns 400ns 500ns tclk validout* release* syscmd sysad validin* wrrdy* ras* ecas* ocas* dwr* dadr ad cstiming* lee leo oee* oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 77 revision 1.1 galileo technology tm f0f0f0f0f 001 000 001 003 f0f0f0f0f fb f 002 0f0f0f0f 0f 0 f 0 f 0 f 004 005 006 007 aaa cpu write burst to 32-bit dram 0ns 100ns 200ns 300ns 400ns 500ns tclk validout* release* syscmd sysad validin* wrrdy* ras* ecas* ocas* dwr* dadr ad cstiming* lee leo oee* oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 78 revision 1.1 galileo technology tm 210123456701 5 5 0 0 f f 0 0 cpu burst read from 32-bit device (acctofirst=4, acctonext=2) 0ns 100ns 200ns 300ns 400ns 500ns tclk validout* release* syscmd sysad validin* wrrdy* ale ads* ad badr ewr* owr* cstiming* le e le o oee* oe o* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 79 revision 1.1 galileo technology tm 0f 10 123 f 0 0f 0 0 4 f0f0 f0 f0f0f f 56 7 2 00 00 5 00 00 5 f f f f f f f f cpu burst write to 32-bit device (adstowr=3, wractive=2, wrhigh=1) 0ns 250ns 500ns tclk validout* release* syscmd sysad validin* wrrdy* ale ads* ad badr ewr* owr* cstiming* lee leo oee* oe o* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 80 revision 1.1 galileo technology tm t7 50 20 50 f f 2 0 0 46 0 2 0ns 100ns 200ns 300ns 400ns 500 tclk validout* release* syscmd sysad validin* wrrdy* ale ad s* ad badr ewr* owr* cstiming lee leo oee* oeo* oeb oe64* leadro cpu 8 bytes read from 16-bit device (acctofirst=4, acctonext=2)
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 81 revision 1.1 galileo technology tm 01 0f 0 210 2 f0f5 f5 0ns 50ns 100ns 150ns 200ns tclk validout* release* sysc md sysad validin* wrrdy* ale ads* ad badr ewr* owr* cstiming lee leo oee* oeo* oeb oe64* leadro cpu 2 bytes write to 16-bit device (adstowr=3, wractive=2, wrhigh=1)
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 82 revision 1.1 galileo technology tm 50 20 50 f f 1 0 0 23 45 6 7 0 2 cpu 8 bytes read from 8-bit device (acctofirst=4, acctonext=2) 0ns 100ns 200ns 300ns 400ns 500ns tclk validout* release* syscmd sysad validin* wrrdy* ale ads* ad badr ewr* owr* cstiming* lee leo oee* oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 83 revision 1.1 galileo technology tm 01 0f a 210 2 fafa f5 cpu byte write to 8-bit device (adstowr=3, wractive=2, wrhigh=1) 0ns 50ns 100ns 150ns 200ns tclk validout* release* syscmd sysad validin* wrrdy* ale ads* ad badr ewr* owr* cstiming* lee leo oee* oeo* oeb oe64* leadro
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 84 revision 1.1 galileo technology tm cpu byte read from pci 0ns 100ns 200ns 300ns 400ns 500ns tclk validout* release* syscmd sysad validin* wrrdy* pclk req* gnt* frame* pad cbe* par devsel* irdy* trdy* lock* stop*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 85 revision 1.1 galileo technology tm cpu 2 bytes write to pci 0ns 100ns 200ns 300ns 400ns tclk validout* releas e* syscmd sysad validin* wrrdy* pclk req* gnt* frame* pad cbe* par devsel* irdy* trdy* lock* stop*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 86 revision 1.1 galileo technology tm cpu burst read from pci 0ns 250ns 500ns 750ns tclk valido ut* release* syscmd sysad validin* wrrdy* pclk req* gnt* frame* pad cbe* par devsel* irdy* trdy* lock* stop*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 87 revision 1.1 galileo technology tm cpu burst write to pci 0ns 100ns 200ns 300ns 400ns 500ns tclk valido ut* release* syscmd sysad validin* wrrdy* pclk req* gnt* frame* pad cbe* par devsel* irdy* trdy* lock* stop*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 88 revision 1.1 galileo technology tm write operation controlled by ready* a l e d a d r [ 1 1 : 0 ] c s [ 3 : 0 ] * c s t i m i n g * e w r [ 3 : 0 ] * o w r [ 3 : 0 ] * l e e l e o o e 6 4 * o e e * o e o * o e b r e a d y * tclk
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 89 revision 1.1 galileo technology tm t c l k a l e d a d r [ 1 1 : 0 ] c s [ 3 : 0 ] * c s t i m i n g * e w r [ 3 : 0 ] * o w r [ 3 : 0 ] * l e e l e o o e 6 4 * o e e * o e o * o e b r e a d y * read operation controlled by ready*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 90 revision 1.1 galileo technology tm tclk ras[3:0]* ecas[3:0]* ocas[3:0]* non staggered refresh
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 91 revision 1.1 galileo technology tm t c l k staggered refresh ecas[3:0]* ocas[3:0]* ras[3:0]*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 92 revision 1.1 galileo technology tm 10.applications: connecting the memory buses in order to connect the memory (dram and devices) correctly, it is necessary to properly choose the system configu- ration. the GT-64010A supports two main configuration modes: without data latches or with data latches. 10.1 working without data latches only systems that do not have 64-bits wide memories can work without latches. in this configuration the only external latch required is for device control and address. notes: 1. dev_adr[21:0] is the output of the control latch connected to ad[23:2], sampled by ale. 2. regardless of data endianess, ecas[0]* and ewr[0]* always correspond to ad[7:0] ecas[1]* and ewr[1]* always correspond to ad[15:8]. ecas[2]* and ewr[2]* always correspond to ad[23:16]. ecas[3]* and ewr[3]* always correspond to ad[31:24]. 3. for load balancing, one can connect owr[3:0]* and ocas[3:0]* as well. connection memory width connect... to... dram address 32-bit dadr[11:0] dram address pins device address 1 32-bit 16-bit {dev_adr[21:2],dadr[2:0]} {dev_adr[21:0],dadr[2:1]} device address pins device address pins 8-bit {dev_adr[21:0],dadr[2:0]} device address pins dram data 2,3 32-bit ad[31:0] dram data pins device data 2,3 32-bit ad[31:0] device data pins 16-bit ad[16:0] device data pins 8-bit ad[7:0] device data pins device control 32-bit or less ad[31:0] ale control latch bit[0] output control latch bit[1] output control latch bit[23:2] outputs control latch bit[27:24] outputs control latch bit[31:28] outputs control latch inputs control latch le becomes bootcs* becomes devrw* becomes dev_adr [21:0] becomes dmaack[3:0]* becomes cs[3:0]*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 93 revision 1.1 galileo technology tm 10.2 working with data latches 10.2.1. 64-bit dram notes: 1. system supports decrement. 2. system is little endian without decrement. 3. system is big endian without decrement. 4. signals can be optionally buffered. connection memory width connect... to... dram address 1 64-bit dadr [ 11:0 ] dadr [ 11:0 ] even latch outputs odd latch outputs leadre leadro even latch inputs odd latch inputs even dram address pins odd dram address pins even latch le odd latch le dram address 2 64-bit dadr [ 11:0 ] 4 dadr [ 11:0 ] odd latch outputs leadro even dram address pins odd latch inputs odd dram address pins odd latch le dram address 3 64-bit dadr [ 11:0 ] 4 dadr [ 11:0 ] even latch outputs leadro odd dram address pins even latch inputs even dram address pins even latch le dram data ( latched ) 8 64-bit ad [ 31:0 ] even latch i/os b side 0 lee oee* oeb 5 ad [ 31:0 ] odd latch i/os b side 0 leo oeo* oeb 5 even latch i/os a side even bank data pins even latch clkab and clkba even latch leab and leba even latch oeba* even latch oeab odd latch i/os a side odd bank data pins odd latch clkab and clkba odd latch leab and leba odd latch oeba* odd latch oeab dram data ( b y pass ) 8 64-bit s y sad [ 31:0 ] 6 s y sad [ 63:32 ] 7 even b y pass latch inputs odd b y pass latch inputs lee leo oe64* even b y pass latch outputs odd b y pass latch outputs even bank data pins odd bank data pins even b y pass latch le odd b y pass latch le even and odd b y pass latches oe*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 94 revision 1.1 galileo technology tm 5. be careful if oeb is programmed at reset to have reverse polarity. 6. sysadc[3:0] from the cpu too, if parity is supported. 7. sysadc[7:4] from the cpu too, if partiy is supported. 8. regardless of endianess, ecas[0]* always corresponds to sysad[7:0] and ad[7:0]. ecas[1]* always corresponds to sysad[15:8] and ad[15:8]. ecas[2]* always corresponds to sysad[23:16] and ad[23:16]. ecas[3]* always corresponds to sysad[31:24] and ad[31:24]. ocas[0]* always corresponds to sysad[39:32] and ad[7:0]. ocas[1]* always corresponds to sysad[47:40] and ad[15:8]. ocas[2]* always corresponds to sysad[55:48] and ad[23:16]. ocas[3]* always corresponds to sysad[63:56] and ad[31:24]. 10.2.2. 32-bit dram it is the same for odd and even bank connections. it is optional to have one bidirectional buffer. notes: 1. example shows even bank choice, but odd bank can be selected instead. 2. regardless of endianess, ecas[0]* always corresponds to sysad[7:0], sysad[39:32] and ad[7:0]. ecas[1]* always corresponds to sysad[15:8], sysad[47:40] and ad[15:8]. ecas[2]* always corresponds to sysad[23:16], sysad[55:48] and ad[23:16]. ecas[3]* always corresponds to sysad[31:24], sysad[63:56] and ad[31:24]. 3. be careful if oeb is programmed at reset to have reverse polarity. 4. signals can be optionally buffered for load balancing. connection memory width connect... to... dram address 4 32-bit dadr[11:0] dram address pins dram data (latched) 1,2 32-bit ad[31:0] even latch i/os b side 0 lee oee* oeb 3 even latch i/os a side even bank data pins even latch clkab and clkba even latch leab and leba even latch oeba* even latch oeab dram data (no latch) 1,2 32-bit ad[31:0] even bank data pins
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 95 revision 1.1 galileo technology tm 10.2.3. 64-bit devices connection memory width connect.. . to... device address 1 6 4 - b i t d a d r [ 2 : 0 ] dadr[2:0] even latch outputs odd latch outputs leadre leadro {dev_adr[21:2], badre[2:1]} 4 {dev_adr[21:2}, badro[2:1]} 4 even latch inputs odd latch inputs become burst address even (badre[2:0]) become burst address odd (badro[2:0]) even latch le odd latch le even bank address pins odd bank address pins device address 2 64-bit dadr[2:0] odd latch outputs leadro {dev_adr[21:2], dadr[2:1]} 4 {dev_adr[21:2}, badro[2:1]} 4 odd latch inputs become burst address odd (badro[2:0]) odd latch le even bank address pins odd bank address pins device address 3 64-bit dadr[2:0] even latch outputs leadro {dev_adr[21:2], badre[2:1]} 4 {dev_adr[21:2}, dadr[2:1]} 4 even latch inputs become burst address even (badre[2:0]) even latch le even bank address pins odd bank address pins device data (latched) 6 64-bit ad[31:0] even latch i/os b side 0 lee oee* oeb 5 ad[31:0] odd latch i/os b side 0 leo oeo* oeb 5 even latch i/os a side even bank data pins even latch clkab and clkba even latch leab and leba even latch oeba* even latch oeab odd latch i/os a side odd bank data pins odd latch clkab and clkba odd latch leab and leba odd latch oeba* odd latch oeab
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 96 revision 1.1 galileo technology tm notes: 1. system supports decrement. 2. system is litttle endian without decrement. 3. system is big endian without decrement. 4. dev_adr[21:0] is the output of the latch connected to ad[23:2], sampled by ale. 5. be careful if oeb is programmed at reset to have reverse polarity. 6. regardless of endianess, ewr[0]* always corresponds to sysad[7:0], sysad[39:32] and ad[7:0]. ewr[1]* always corresponds to sysad[15:8], sysad[47:40] and ad[15:8]. ewr[2]* always corresponds to sysad[23:16], sysad[55:48] and ad[23:16]. ewr[3]* always corresponds to sysad[31:24], sysad[63:56] and ad[31:24]. owr[0]* always corresponds to sysad[39:32] and ad[7:0]. owr[1]* always corresponds to sysad[47:40] and ad[15:8]. owr[2]* always corresponds to sysad[55:48] and ad[23:16]. owr[3]* always corresponds to sysad[63:56] and ad[31:24]. device data (bypass) 6 64-bit sysad[31:0] sysad[63:32] even bypass latch inputs odd bypass latch inputs lee leo oe64* even bypass latch outputs odd bypass latch outputs even bank data pins odd bank data pins even bypass latch le odd bypass latch le even and odd bypass latches oe* device control 64-bit ad[31:0] ale control latch bit[0] output control latch bit[1] output control latch bit[23:2] outputs control latch bit[27:24] outputs control latch bit[31:28] outputs control latch inputs control latch le becomes bootcs* becomes devrw* becomes dev_adr [21:0] becomes dmaack[3:0]* becomes cs[3:0]* connection memory width connect.. . to...
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 97 revision 1.1 galileo technology tm 10.2.4. 32-bit or less devices it is optional to have one bidirectional buffer. notes: 1. dev_adr[21:0] is the output of the latch connected to ad[23:2], sampled by ale 2. bidirectional latch is optional for buffering, and either odd or even bank can be chosen. this example shows an even bank connection. 3. regardless of endianess, ewr[0]* always corresponds to sysad[7:0] and ad[7:0] regardless of endianess. ewr[1]* always corresponds to sysad[15:8] and ad[15:8] regardless of endianess. ewr[2]* always corresponds to sysad[23:16] and ad[23:16] regardless of endianess. ewr[3]* always corresponds to sysad[31:24] and ad[31:24] regardless of endianess. 4. be careful if oeb is programmed at reset to have reverse polarity. connection memory width connect... to... device address 1 32-bit 16-bit 8-bit {dev_adr[21:2], dadr[2:0]} {dev_adr[21:0], dadr[2:1]} {dev_adr[21:0], dadr[2:0]} device address pins device address pins device address pins device data (latched) 2,3 32-bit or less ad[31:0] or [15:0] or [7:0] even latch i/os b side 0 lee oee* oeb 3 even latch i/os a side even bank data pins even latch clkab and clkba even latch leab and leba even latch oeba* even latch oeab device data (no latch) 32-bit or less ad[31:0] or [15:0] or [7:0] device data pins device control 32-bit or less ad[31:0] ale control latch bit[0] output control latch bit[1] output control latch bit[23:2] outputs control latch bit[27:24] outputs control latch bit[31:28] outputs control latch inputs control latch le becomes bootcs* becomes devrw* becomes dev_adr [21:0] becomes dmaack[3:0]* becomes cs[3:0]*
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 98 revision 1.1 galileo technology tm 11. applications: system configurations 11.1 minimal system configuration a minimal system configuration is shown below. it includes an 8-bit wide boot rom, a 32-bit wide dram, and a pci interface to industry standard i/o devices. this configuration can be appealing to applications that need high perfor- mance and are limited to a minimal board space. r4xxx gt- 64010a dram boot rom 8 32 pci cs* dadr[11:0] ecas*[3:0] ras*[0] dwr* ad[31:0] pci i/o pci i/o ale latch or cstiming* sysad bootcs* dev_adr [21:2] dadr[2:0] 32 64 32
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 99 revision 1.1 galileo technology tm 11.2 typical system the high performance system shown below includes 64-bit wide memories and 32-bit i/o devices on the pci bus. the system includes flash for storing code and data, and dram as main memory. in this system data can be moved via dma or pci master accesses between the pci bus and the flash or dram at full bus bandwidth, at 200 mbytes per second. the cpu can read from the dram at peak bandwidth of 200mbytes per second. cpu writes have peak band- width of 400mbytes per second for all devices through the GT-64010A on-chip write buffer. pci slave pci master dram flash 373 373 501 373 pci ad[31:0] r4xxx GT-64010A sysad[63:0] or oe64*, lee, leo d[63:0] dadr[11:0] leadr0, leadre control signals ed[31:0] od[31:0] dadr[2:0] dev_adr[21:2] ad[31:0] ale cstiming* lee, oee*, oeb d[31:0] bootcs* cs* 32 64 32 32
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 100 revision 1.1 galileo technology tm 11.3 interface to asynchronous devices in this case, we show the connectivity between the GT-64010A and 64 bit-wide standard memory devices (e.g. sram). in this example the latches selected are industry standard fct16501for data, fct16373 for the address, and fct16373 for the burst address for the odd bank. the data latches that interface to the ad bus are used to interleave the data in read and write access from the GT-64010A and enable data rate of one data per cycle at 50mhz (200 mbytes per second peak rate). the data latches that interface the sysad bus are used only in one direction in cpu reads. the sysad latches enable low latency to first word and up to 400 mbytes per second bandwidth in cpu burst reads. fct16373 logic chips are used to latch the address, the cs* and the devrw*for the devices. the latch for the odd bank burst address is needed for the address interleaving. this system configuration is for little endian, no decre- ment. lee oe e* ale leo oeo* cs[0]* cs[0]* ad[31:0] oeb oeb ewr[3:0]* owr[3:0]* dadr[2:1] badr[2:1] devoe* oe64* leo lee flash eprom sram rom flash eprom sram le 373 b a 373 b a le oe* oe * 373 odd bank even bank rom 373 leadro gt- oe64* devoe* or cstiming* devrw* 64010a r4xxx sysad[63:0] sysad[31:0] sysad[63:32] dev_adr[21:0] dadr[2:0] dev_adr[21:0] oeab leab leba oeba * 501 b a oeab leab leba oe ba * 501 b a 64 32 32 32 32 32 or
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 101 revision 1.1 galileo technology tm 11.4 interface to dram the dram and the device interface in a typical system share the same data latches and address latches. in this exam- ple the dram is 64 -bit wide and the even and odd banks share the same ras[0]* pin. address for the odd bank is driven from an fct16373 latch which is controlled by leadro. the data latches used in this example are fct16373 for the interface to the sysad and fct16501 to the ad bus. this system configuration is for little endian, no decre- ment. leadro eca s[3:0]* ocas[3:0]* dwr* dwr* dadr[11:0] ras[0]* ras[0]* odd bank even bank lee oee* leo oeo* oeb oeb oe64* leo lee oe64* sysad[63:0] le 373 b a 373 b a le oe* oe* 373 ad[31:0] gt- r4xxx sysad[63:32] sysad[31:0] dram dram 64010a oe ab leab leba oeba * 501 b a oeab leab leba oeba * 501 b a 64 32 32 32 32 32
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 102 revision 1.1 galileo technology tm 11.5 a system with parity in this case, the fct16511 is used to generate parity for all the write accesses to the devices and the dram. in a cpu read access the fct16511 w ill check parity and w ill assert the parerr* si gnal when an error is detected. the gt- 64010a w ill indicate to the cpu that the retur ned data is erroneous via syscmd[5] and w ill interrupt the cpu if the bank that the cpu read from was programmed to have parity integrity checks. the GT-64010A also asserts syscmd[4] to indicate to the cpu if the read access was from an address with parity integrity so that the cpu w ill check parity internally as well. in pci read accesses, an active parerr* to a bank that has parity integrity, w ill cause an assertion of perr* on the pci. notice that with the fct16511 the oeab* polarity is active low, as opposed to the fct16501, and thus oeb from the GT-64010A should be programmed accordingly at reset. this system configuration is for little endian, no decrement. leadro e cas [3:0]* ocas[3:0]* dwr* dwr* dadr[11:0] ras[0]* ras[0]* odd bank even bank lee oee* leo oeo* oeb oeb oeab* leab leba oeba * b a oe64* leo lee oe64* sysad[63:0], sysadc[7:0] le b a b a le oe* oe* 841 ad[31:0] gt- 841 841 511 parerr* pera* 32 32 36 36 36 72 36 36 r4xxx sysad[31:0], sysadc[3:0] 64010a sysad[63:32], sysadc[7:4] dram dram oeab* leab leba oeba * b a 511 pera* 36
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 103 revision 1.1 galileo technology tm 12. packaging 256 lead pqfp package outline symbol millimeters min. nom. max. a 1 0.05 0.25 0.50 a 2 3.17 3.32 3.47 b 0.13 0.18 0.23 c 0.09 0.20 d 27.90 28.00 28.10 e 27.90 28.00 28.10 e0.40 hd 30.35 30.60 30.85 he 30.35 30.60 30.85 l 0.45 0.60 0.75 l 1 1.30 y0.08 q0 10 a 1 he e hd d b a 2 l l 1 0.07(0.003) m y gage line 0.25 e c pin rotation
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 104 revision 1.1 galileo technology tm side view bottom view top view 272 bga package outline drawing all dimensions in millimeters ner 27.00 + 0.20 24.00 + 0.70 0.00 16.10 ref 27.00 + 0.20 24.00 + 0.70 0.00 16.10 ref printed wire board mold compound 0.60 + 0.10 0.36 + 0.04 30 o typ. all sides 1.17 + 0.05 2.13 + 0.19 die solder ball printed wire board mold compound a y w v u t r p n m l k j h g f e d c b pin 1 corner 1.27 1.27 1.44 ref 1.44 ref 20 2 18 16 14 12 10 8 6 4 1 19171513119753
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 105 revision 1.1 galileo technology tm 13.appendices 13.1 GT-64010A behavior with little/big endian data formats 13.1.1. background there are two bits in the GT-64010A which control byte swapping. one is located in the cpu interface units mode reg- ister (0x000) bit 12, the other in pci interface units command register (0xc00) bit 0. both bits are given the same value as sampled at reset via pullup/pulldown on interrupt* pin. both can be otherwise programmed after reset is deasserted. as a master rule, if both bits are set to 1, the GT-64010A assumes little-endian data format and no byte swapping is done within the device. 13.1.2. nomenclature w - word, 32 bit data. (r4600 terminology) dw - double-word, 64 bit data. (r4600 terminology) even address - address of which a[2] == 0. in little-endian format this address points to the least significant w of a dw, in big-endian format this address points to the most significant w of a dw. odd address - address of which a[2] == 1. in little-endian format this address points to the most significant w of a dw, in big-endian format this address points to the least significant w of a dw. even word - least significant w of a dw. odd word - most significant w of a dw a) bit 12 of the cpu interface units mode register (0x000) affects the following: a1) set to 1 (little-endian mode) - no byte swapping within the cpu interface unit on any data transfer. a2) set to 0 (big-endian mode) - byte swapping of data transfers to/from GT-64010A internal registers (including configuration data register, 0xcfc). - no byte swapping of data transfers of which the source/target is external. b) bit 0 of the pci interface units command register (0xc00) affects the following: b1) set to 1 (no byte swapping) - no byte swapping within the pci interface unit of any data transfer. b2) set to 0 (byte swapping) - no byte swapping of data transfers to/from pci interface units internal registers. - byte swapping of data transfers of which the source/target is external c) here is a table which describes all combinations of the resources and swapping bits with a sample data. (cpu bit means the cpu interface units mode register (0x000) bit 12, pci bit means the pci interface units command register (0xc00) bit 0). the sample data is 04030201h.
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 106 revision 1.1 galileo technology tm swap bits (cpu bit:pci bi t) 13.2 address decoding 13.2.1. cpu interface units address decode an address generated by the cpu is decoded within the cpu interface unit as follows: - address bits [35:28] are checked for equality to cpu interface units low decode registers bits [14:7] - address bits [27:21] are checked to be greater or equal to cpu interface units low decode registers bits [6:0] - address bits [27:21] are checked to be less or equal to cpu interface units high decode registers bits [6:0] an address is said to be a hit when a match occurs in all three criterias for the same low and high decode register pair. 13.2.2. dma address decode the dma uses three types of address: source , destination and pointer . (pointer address is used only for chained mode) all three are decoded the same way as follows: - address bits [31:28] are checked for equality to cpu interface units low decode registers bits [10:7] - address bits [27:21] are checked to be greater or equal to cpu interface units low decode registers bits [6:0] - address bits [27:21] are checked to be less or equal to cpu interface units high decode registers bits [6:0] an address is said to be a hit when a match occurs in all three criterias for the same low and high decode register pair. 13.2.3. pci interface units address decode an address generated by a pci master is decoded within the pci interface units slave as follows: - address bits for which the corresponding bits in the size registers are 0 are checked for equality to the corre- resource 11 00 01 10 internal registers (cpu access) 04030201 01020304 01020304 04030201 internal registers (pci access) 04030201 04030201 04030201 04030201 internal pci configuration registers (cpu access) 04030201 01020304 01020304 04030201 internal pci configuration registers (pci access) 04030201 04030201 04030201 04030201 external pci configuration registers 04030201 04030201 01020304 01020304 memory (dram and devices) (cpu access) 04030201 04030201 04030201 04030201 memory (dram and devices) (pci access) 04030201 01020304 04030201 01020304 cpu to pci (except external pci config- uration registers) 04030201 01020304 04030201 01020304
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 107 revision 1.1 galileo technology tm sponding bits of the base registers. an address is said to be a hit when a match occurs with a certain base register in all bits pointed by its respective size register. example : ras[3:2] bank size register = 03fffh ---> address bits to compare are: ad[31:26] (1s are dont care) therefore, an address of which bits [31:26] equal ras[3:2] base address registers bits [31:26] is considered a hit and w ill access ras[3:2] space. 13.2.4. dram/device interface units address decode the dram/device interface unit receives an address from either the cpu interface unit, pci interface unit or dma. this address has already been decoded primarily in the originating unit to be targeted either to ras[1:0], ras[3:2], cs[2:0], cs[3] & bootcs or internal spaces. the dram/device interface unit now further decodes the incoming address as follows: ? address bits [27:20] are checked to be greater or equal to dram/device interface units low decode regis- ters bits [7:0] ? address bits [27:20] are checked to be less or equal to dram/device interface units high decode registers bits [7:0] an address is said to be a hit when a match occurs in both criterias for the same low and high decode register pair. 13.3 jtag - signal ordering the following list describes the ordering of the GT-64010A signals in the boundary scan chain:
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 108 revision 1.1 galileo technology tm note: oe* suffix to outputs/bidirectionals denotes the respective active low output-enable control. signal name chain position signal name chain position req* 0 dadr[0]/badr[0] oe* 8 req oe* 1 dadr[1]/badr[1] 9 gnt* 2 dadr[2]/badr[2] 10 pclk 3 dadr[2]/badr[2] oe* 11 rst* 4 dadr[3]/ewr[0]* 12 int* 5 dadr[3]/ewr[0]oe* 13 intoe* 6 dadr[6:4]/ewr[3:1]* 16:14 dadr[0]/badr[0] 7 dadr[6:4]/ewr[3:1] oe* 17 dadr[10:7]/owr[3:0]* 21:18 oee* 88 dadr[10:7]/owr[3:0]oe* 22 oeeoe* 89 dadr[11]/ads* 23 oeb 90 dadr[11]/adsoe* 24 oeb oe* 91 ras[3:0] * 28:25 leadro 92 ras[3:0] oe* 29 leadro oe* 93 ocas[3:0]* 33:30 leadre/dmareq[2]* 94 ocas[3:0] oe* 34 leadre/dmareq[2]oe* 95 ecas[3:0]* 38:35 dmareq[1]*/parerr* 96 ecas[3:0] oe* 39 dmareq[0]*/ready* 97 dwr* 40 sysad[56:63] 105:98 dwroe* 41 sysad[56:63]oe* 106 ad[0]/bootcs* 42 sysad[48:55] 114:107 ad[1]/devrw* 43 sysad[48:55]oe* 115 ad[7:2 ] 49:44 sysad[40:47] 123:116 ad[0]/bootcsoe*, ad[1]/devrwoe*, ad[7:2 ] oe* 50 sysad[40:47]oe* 124 ad[15:8 ] 58:51 sysad[32:39] 132:125 ad[15:8 ] oe* 59 sysad[32:39]oe* 133 ad[23:16 ] 67:60 release* 134 ad[23:16 ] oe* 68 wrrdy* 135 ad[27:24]/dmaack[3:0]* 72:69 wrrdyoe* 136 ad[31:28]/cs[3:0]* 76:73 validin* 137 ad[27:24]/dmaack[3:0]oe*, ad[31:28]/ cs[3:0]oe* 77 validinoe* 138 cstiming* 78 validout* 139
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 109 revision 1.1 galileo technology tm cstimingoe* 79 sysad[24:31] 147:140 ale 80 sysad[24:31]oe* 148 ale oe* 81 sysad[16:23] 156:149 leo 82 sysad[16:23]oe* 157 leooe* 83 tclk 158 lee 84 sysad[8:15] 166:159 leeoe* 85 sysad[8:15]oe* 167 oeo* 86 sysad[0:7] 175:168 oeooe* (spelling excercise...) 87 sysad[0:7]oe* 176 syscmd[3:0] 180:177 perroe* 220 syscmd[3:0]oe* 181 lock* 221 syscmd[8:4] 186:182 stop* 222 syscmd[8:4]oe* 187 stopoe* 223 interrupt* 188 devsel* 224 interruptoe* 189 devseloe* 225 hit/dmareq[3]* 190 trdy* 226 oe64* 191 trdyoe* 227 oe64oe* 192 irdy* 228 pad[3:0] 196:193 irdyoe* 229 pad[3:0]oe* 197 frame* 230 pad[7:4] 201:198 frameoe* 231 pad[7:4]oe* 202 cbe[2]* 232 cbe[0]* 203 pad[19:16] 236:233 pad[11:8] 207:204 pad[19:16]oe* 237 pad[11:8]oe* 208 pad[23:20] 241:238 pad[15:12] 212:209 pad[23:20]oe* 242 pad[15:12]oe* 213 idsel 243 cbe[1]* 214 cbe[3]* 244 par 215 cbe[3:0]oe* 245 paroe* 216 pad[27:24] 249:246 serr* 217 pad[27:24]oe* 250 serroe* 218 pad[31:28] 254:251 perr* 219 pad[31:28]oe* 255 signal name chain position signal name chain position
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 110 revision 1.1 galileo technology tm notes: 1. sysad ordering in the boundary scan chain is reversed.i.e., for ascending chain order, sysad lane significance is in descending order. 2. the tribyp opcode is not implemented. if tri-stating all GT-64010A outputs and bidirectionals is needed, use the extest opcode to disable all oe* controls in the chain. 13.4 connecting the GT-64010A without a cpu when the GT-64010A is used in a system without a cpu, the cpu interface units inputs should be pulled up, i.e., sysad, syscmd, validout*, release* and hit. 13.5 disabling jtag if the jtag is not to be used, the following should be pulled-up/down: jtrst* - pulldown jtdi - pullup jtms - pulldown jtclk - pulldown 13.6 dram address partitioning this appendix includes an explenation on how the dram address is formed in respect to the xkrefresh that the gt64010a is programmed to. following is a table showing how the address is split into row and column addresses during ras phase and cas phase. notes: the table refers to 32 bit dram configuration. for 64 bit configuration, 4...2 is c hanged to 4 ...3. example: for 1krefresh the dadr bus will look as follows: during row phase, dadr[9:0] w ill hold sysad[14:5] (or pad[14:5]). during column phase, dadr[11:0] = {sysad[23:21],sysad[16:15],sysad[20:17],sysad[4:2]}.(or pad...) krefresh # of row bits row bits column bits 1/2 9 5...13 22...20 16...14 19...17 4...2 1 10 5...14 23...21 16...15 20...17 4...2 2 11 5...15 24...22 16 21...17 4...2 4 12 5...16 25...17 4...2
GT-64010A system controller with pci interface for r4xxx/r5000 family cpus 111 revision 1.1 galileo technology tm 14 revision history table 1: revision history document type revision number date comments preliminary rev. 1.0 7/96 first revision of preliminary revision for g eneral distribution. preliminary rev. 1.1 12/96 section 5.12 : chan g ed 4 24bit timers to 3 24bit and 1 32bit timer. section 8.3 : chan g ed operatin g current from 280ma to 400ma. section 8.4 : added thermal packa g e characteristics for 256pqfp. section 8.5 : added thermal packa g e characteristics for 272 bga section 14 : updated revision histor y .

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